This is a log of various changes and progress to the CFT project. This is a long-term project built in my Copious Free Time, hence the name. It's a self-designed, self-built Sixties-style 16-bit mini computer built out of 74xxx integrated circuits. You may be interested in having a look at the full discussion of the CFT computer. This page only documents progress, and it's mostly for myself.
CFT Project Log
Dem VDU Timing Blues
I'm not dead, just trying to puzzle out insidious timing issues with the CFT's video card. Which is about the same, really. Who would have thought that designing a CPU is easier than a properly timed CRTC!
I'm now on the fourth iteration of the video card design and I'm designing on the basis of easy timing adjustments (mainly horizontal and vertical position) at the cost of chip count and simplicity. If it's this bad in Verilog, I can only guess how bad it'd get in hardware, so might as well prepare.
Interesting Realisations
It seems making your own processor isn't entirely like making a ‘proper’ industrial design. In the industry, minimising chip count is one of many metrics of a successful design. On the CFT, it might not be. And it looks like actually using as much of the board estate with versatile hardware is actually better for the CFT. There are two examples of this.
Digital Storage Oscilloscope
I was hoping it wouldn't come to this quite yet, but it has. I need to splurge on a Digital Storage Oscilloscope (DSO). I already have a traditional, cathode ray tube oscilloscope, but there are two problems with it: one, it's a 1 MHz unit (and that's stretching it), which can't hope to diagnose problems occurring at frequencies such as those used on the CFT. Two, it's not a storage oscilloscope, so any waveforms it captures are gone before I can have a look at them.
First setback
Looks like I've experienced my first serious setback. I powered up the backplane, resistors and all, and it looked okay, apart from the heating terminating resistors. There are 152 sets of them, each forming a voltage divider — so 300 resistors in total. Signals are tied to ground using 470Ω resistors, and to +5V using 330Ω. Do the math, and we get a composite resistance of 800Ω/152=5.263Ω. That's 0.95A, and at 5V, that's 4.75W and it's all converted into heat.
Construction Time (not again)!
It's been a busy time with work and life, but I found just about enough time to start construction of the CFT. This is a progress report on the first stages of construction, getting used to the prototyping techniques, and forming a construction routine to help avoid mistakes. The debugging board is done and tested, though the wiring isn't as elegant as I'd like. The memory board is currently under construction, and potential problems have been found with the backplane and its termination.
The Calm Before the Storm?
The big news for now is that I've just gone past the point of no return: I've ordered the first batch of components needed to start construction.
That Damned Debugging Card
When I first started coding unit tests for the CFT, I was testing parts of the processor in Verilog. To allow for arbitrary testing, I made a virtual ‘debugging interface’. You could OUT to one of its decoded I/O addresses, and it would send out (to an assumed host computer) the value of the accumulator in various formats (hex, decimal, character), as well as various other signals (assertion failed, success, etc). This allowed my unit testing framework to look for patterns in the Verilog simulation output, and easily test the CPU.
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