I think this took me around a man-week of routing, but it's finally done. Sort of. The Control Unit is routed. In order to make the traces fit, I've had to remove most of the pull-up resistors (they'll go on the clock board), the read unit decoder (it'll also go to the clock board) and the ALU unary/binary op decoder (which will go where it belongs, on the ALU board). The OPIF signals are now local to the control unit. Nothing else needs them in the control part of the processor, so I've removed them from the Control Bus to make room for the three least-significant bits of the IR, which are needed.

This obviously snowballed into a load of changes to various other Eagle files and documentation.