I've finally managed to route the front panel controller board. It took a while longer because (shock!) I did pulled yet another 180° turn on the bus layout. I located a cheap(-ish) source for the wire-wrap female headers, which means I can go back to stacking the processor boards together without needing two separate DIN-41662 buses. Instead, the required signals (and only the required signals) travel from board to board via the female headers. This comes at a small cost to board estate, but simplifies a lot of other things, including the processor routing.

Since there's now only a single bus, the front panel controller is now a single board, not two (one for the Control Bus, one for the Expansion Bus). There will have to be extra connectors added to other boards, though.

The controller board offers the following features:

• The Run/Stop state machine which controls the processor's halt states and clock.
• The memory cycle sequencer used when the examine/deposit switches are operated.
• The front panel system device decoder.
• The output register (a 16-bit register used as an output device on the front panel).
• The switch register (the values of the 16 switches on the front panel, used as an input device).
• The DIP switch register, which reads the value of two banks of 8 DIP switches, used to provide boot-time configuration data.
• The HALT operation, which stops the clock and halts the processor programmatically.

In other news, I also found some time to work on the CFT Assembler, which now supports file inclusions and multi-line macros. I'm particularly happy with the macro feature, although the design precludes forward definitions (aka prototypes) and recursion.