This update is months overdue, which is why it's so huge. I've been lacking time. Given the name of the project, this is very ﬁtting. There's still been a lot of work. I'll try to take things one by one.
The CFT computer has a new set of features now, based on the work so far:
- 16-bit extensible architecture inspired by the PDP-8
- Processor speed of up to 4 MHz.
- Processor implemented in CMOS DIP and some PLCC parts.
- The UARTs and ROMs are the the most complex single-components in use on the ﬁnal computer.
- 64 kWord address space.
- 21-bit banked address space. 512 kW RAM, 512 kW Flash ROM, programmable in-circuit (a write-protect jumper is also provided).
- Two or four serial ports. One designed to run at TTL levels.
- Two or four IDE disks.
- Timer board with three or six programmable timers.
- Real-Time Clock and 2 kByte NVRAM.
- Interrupt controller with 8 shareable interrupts.
- Ethernet card using the WIZ5100 module. This allows both rapid prototyping and the full flexibility of an Ethernet MAC.
- Experimental PS/2 keyboard interface.
- The ﬁrst rudiments of a video card.
- A front panel with a staggering 122 lights and 31 switches.
I have collected the various schematics into a huge drawing of 43 A3 sheets. Some will go away as the front panel schematics are redrawn, but more may be added. The video board will probably occupy a number of sheets in itself.
The Forth interpreter have advanced to a good portion of an operating system. The interpreter is complete, the compiler is mostly complete (there are a few lingering bugs with multi-line compilation), and the Forth system can boot up, detect devices, initialise the system and provide a user interface.
Most of the I/O part of the emulator has been re-written from scratch to allow for additional hardware to be coded. So far, I have trivial implementations of IDE interfaces, UARTs, the Memory Banking Unit, the RTC and the NVRAM.
There have been a number of improvements to the processor proper, including stubs for further expansion. A few signals have been converted to open-drain ones so that extension cards can drive them to provide custom processor behaviours.
Since I have large Flash RAMs and the microcode is tiny, I reserved some pins for future banking expansion so that multiple microcode sets can run on the same hardware.
There's also a facility wait states which can be used for a number of tricks
I found a couple of little bugs in the microcode, and rewrote it so that memory and I/O access cycles are two clock ticks long. Wait state handling happens at a sub-clock rate.
Yes, I changed my mind about the prototyping again. Printing all those one-oﬀ PCBs became too expensive, so I'm once more forced to use pad-per-hole prototyping boards. I'll try building a couple of the boards and see how it goes.
I also decided to start top-to-bottom. I'm not proﬁcient in electronics, and I can't aﬀord to blow too much hardware. Rather than building a front panel and then implementing bits of the computer in an excruciatingly slow, careful, deliberate fashion, here's the new plan: get an FPGA development board.
The board makes it possible to describe the entire computer as a behavioural model. This can then be tested on-board, with the existing unit tests running on the board (possibly downloaded via USB or Ethernet for huge time savings).
Once the behavioural design is sane, I can start to build external hardware: ﬁrst the the serial and IDE boards. As components are added to the computer, the respective components on the dev board are disabled. Eventually, the components of the processor will be in place, and the dev board can either be removed, or it can remain: it can implement the complex ‘debugging board’ (which is only present in the emulator due to its complexity), act like a logic analyser, or help design and debug the video card.
On top of it, having a small dev board means I can test the hardware computer on the move (since I'm becoming more and more of a nomad these days).
It also means I'll have an FPGA version of the CFT capable of being embedded elsewhere. Since most of the computer can probably ﬁt on a single FPGA, I could make a toy version of the hardware.
And, at less than USD 200, it's a considerably cheaper option than starting from scratch.
The Ethernet card is a a new, quite simple board meant to accommodate a WIZ5100 module. The module helps early prototyping: it can talk IPv4 on its own and provide up to four simultaneous TCP or UDP connections. For more advanced use, the intelligent section can be disabled, and the module behaves like a self-contained ethernet MAC.
The card only requires two ICs and headers for the module, plus an optional 12V to 3.3V regulator: the module works at 3.3V but is 5V tolerant. A PHY is included, as well as an Ethernet jack with transformers.
This is such a simple design, that sense dictates some added hardware is included to make it a full card. Perhaps some GPIO. With an extra IC in the address decoding section there can be four 16-bit I/O ports for this: that's 64 outputs plus 64 inputs. More than adequate for, say, a parallel printer interface and some User I/O pins. This'll need an additional eight ICs.
These ones are very, very experimental at the moment. The idea is to prototype a video device for the CFT as its last user interface (in addition to the front panel, serial communications, and maybe Telnet.)
This is a pretty ambitious project in itself, so I'll do it last.
The video board is meant to take advantage of the 16-bit nature of the CFT design and the abundance of huge memory ICs. I intend to implement a single 640×400 mode, relatively easy to do with HC (and some AC) logic.
Within the 640×400 frame, diﬀerent height character cells may be displayed (all characters will have 8 columns). With an 8×16 cell, we get an 80×25 text mode. With an 8×8 cell, we get 80×50 text or block graphics (not too shabby: many home micros of the 80s had 64×50 block graphic modes). With an 8×4 cell, ﬁner control of the block graphics may be attained. And with an 8×1 cell and a suitable font, we get bitmap graphics — the famous TMS9918 did it the same way.
Character generation memory is probably going to be static RAM. Given how cheap static RAM is, it's likely this will be a 8×512 kByte IC (4 Mbits). This allows a serious 32,768 diﬀerent 16-row character patterns. Since it's RAM, software can be used to set these to whatever is required. Given the space, bits can be set aside for double-width and double-height characters and the hardware will only need an additional two OR gates to make it work.
There's a separate colour plane RAM, and this can allow 64 colours: 2×6 bit ﬁelds for foreground and background. In semigraphics modes, each character cell has its own pair of colours. In bitmap graphics, each 8×1 cell has its own pair of colours.
Video RAM will be 64 kWords, 32 for each plane, probably with windowed access from main memory.