It's hot here. Hot enough to make thinking difficult at times. I've been working on the wait state and cycle stepping hardware today, and I spent about half an hour trying to think about some properties of the clock generator. The heat works as an excuse, but it's clear the clock generator was too complex for simple thinking. I need it simple, or mistakes will happen.

So I sat down and simplified the design. In the process, the geometry of the clocks changed. The CFT used to have four 50% duty cycle clocks, plus some bizarre composite clocks with various duty cycles and phase differences.

We now have four non-overlapping 75%-duty cycle clocks, and that's it. As a result, the clock generator is much simpler (just four 74xxx ICs, no delay lines, no jumpers to set), and the processor cycle is now cleanly split into four stages, T1–T4:

Stage T1:

The microprogram counter increments, generating a new microprogram address. A microcode memory lookup begins.

Stage T2:

The microcode memory lookup concludes. With 70 ns ROMs, the second phase must be used to wait for the signals to stabilise. As this happens, the decoding unit (which is asynchronous) decodes the micro-instruction vector into read enable signals and write strobe enable signals for the various units.

Stage T3:

One of various things can happen at this point.

• If no data transfer is required by the micro-instruction, the processor goes idle.
• If a data transfer between internal processor units is needed, the unit to be read from drives the IBUS with its data.
• If a memory or I/O read is requested, MEM or IO is asserted as appropriate. R is also asserted at this time. This instructs the memory or peripheral to select chips and initiate a read cycle. During this phase, the memory or peripheral may signal a WS to temporarily delay the onset of the next phase.
• If a memory or I/O write is requested, MEM or IO is asserted as appropriate. This instructs the memory or peripheral to select chips and initiate a write cycle. Data is driven onto the IBUS, and the \DBUS{} is connected to the IBUS to provide valid data for the external device. During this phase, the device may assert \ns{WS} to temporarily delay the onset of the next phase.

Stage T4:

One of various things can happen at this point.

• If no data transfer is required by the micro-instruction, the processor remains idle.
• If a data transfer between internal processor units is needed, the appropriate write enable signal is asserted at this point, and the unit latches data from the \IBUS. This also happens for memory or I/O reads.
• If a memory or I/O write is requested, \ns{W} is asserted. The external device latches or clocks data accordingly.

The clock generator outputs all four clock phases CLK1 to CLK4, plus two active-low signals to detect when stages T1–T2 and T3–T4. They can be used to detect when the processor is using the bus, so memory accesses may be multiplexed (for instance, to allow zero wait state access to the VDU framebuffer). T34 replaces GUARD on the CFT expansion bus.

Another positive side-effect of the new clocks is that bus contention is all but eliminated with no additional signals or logic. In fact, quite a few ICs that dealt with guard pulse generation and handling have been removed now.

Interestingly, despite the seemingly fundamental changes to the clock geometry, most of the processor is asynchronous, and was unaffected. It was just a matter of refactoring some Verilog code and renaming some schematic signals.