BedroomLAN

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CFT Project Log

This is the project log of the CFT project, updated as the project is being worked on. The changes aren't always published immediately, though. It's a bit dry, but it's probably your best bet for progress information!

June 2016

2016-06-12: Documentation, CFT Book

Writing documentation for the DFP. Started documenting the hardware, including Sketchup renders, PCBs, assemblies etc.

2016-06-12: Bugs, Testing, Debugging Front Panel

Discovered and fixed a minor bug in the DFP firmware (HALT instruction not being honoured while multistepping or tracing). Colourised error messages.

2016-06-11: Documentation, CFT Book

Writing documentation for the DFP.

2016-06-11: Bugs, Testing, Debugging Front Panel

Fixed a number of minor bugs in the DFP firmware.

2016-06-10: Documentation, CFT Book

Writing documentation for the DFP.

2016-06-10: Bugs, Testing, Debugging Front Panel

Fixed a number of minor bugs in the DFP firmware. Reflashed the physical DFP and performed a few tests on it.

2016-06-06: Documentation, CFT Book

Writing documentation for the DFP.

2016-06-06: Bugs, Testing, Debugging Front Panel

Fixed a number of minor bugs in the DFP firmware.

2016-06-05: Documentation, CFT Book

Writing documentation for the DFP.

2016-06-04: Documentation, CFT Book

Writing documentation for the DFP.

May 2016

2016-05-30: Documentation, CFT Book

Writing documentation for the DFP.

2016-05-30: Testing, Debugging Front Panel

Worked on the DFP testing tool.

2016-05-29: Documentation, CFT Book

Writing documentation for the DFP.

2016-05-28: Documentation, CFT Book

Writing documentation for the DFP.

2016-05-21: Coding, Emulator

Finished pseudo-TTY code, so the emulator can be used to develop tests for the real, live CFT. The emulated DFP is still not fully implemented, but it's close enough to test things. Fixed minor bugs.

2016-05-21: Bugs, Testing, Debugging Front Panel

Fixed a number of minor bugs in the DFP firmware just by testing communications with the testing tool.

February 2016

2016-02-14: Documentation, CFT Book

Completed first update of the theoretical description chapter. Needs to be re-organised heavily.

2016-02-13: Documentation, CFT Book

Worked on the web edition of the Theoretical Description chapter.

2016-02-12: Documentation, CFT Book

Worked on reference resolving code, improved markup framework. Worked on the web edition of the Theoretical Description chapter.

2016-02-08: Documentation, CFT Book

Worked on the web edition of the Theoretical Description chapter.

2016-02-07: Documentation, CFT Book

Worked on the Web version of the documentation. Redid the Assembler chapter and worked on formatting code and styling. Debugged plenty of issues with the TeX to HTML conversion. Fixed spelling mistakes. Brought some of the content up to date.

2016-02-07: Documentation, CFT Book

Worked on the web edition of the Theoretical Description chapter.

2016-02-06: Documentation, CFT Book

Worked on the Web version of the documentation. Redid the Programming Model chapter. Worked on the styling. Added a little information and corrected mistakes.

2016-02-01: Coding, Emulator

Fixed bugs from previous day. The run/stop logic works fine now. Working on more integration of DFP features.

January 2016

2016-01-31: Construction, Hardware, Processor Board 1

Fixed minor layout issues on G PB1 board.

2016-01-31: Coding, Emulator

Added front panel and bus interrupt support to the emulated DFP. Working on run/stop logic and bus command integration. It's more complex than it looks because of the necessity for synchronisation and thread-safety. I may have to simplify things, but can't really change the firmware code so the separate thread is here to stay.

2016-01-30: Construction, Hardware, Processor Board 1

Verifying Rev G PB1 schematic and preparing to have it manufactured.

2016-01-30: Coding, Emulator

Added Switch Register support to the emulator and improved the virtual front panel. Continuing to implement virtual DFP integration.

November 2015

2015-11-15: Coding, Emulator

Worked on virtual reset circuitry. Thread synchronisation can be problematic for this stuff, since the DFP runs on its own thread. Using a system of simple messages to the emulator thread.

2015-11-14: Coding, Emulator

Worked out the previous ‘deadlock’ issue: it was OS blocking because the Emulator was opening a debugging pseudo-TTY which wasn't being read from. Once the OS PTY buffer got full, writes blocked blocking the entire DFP thread (but not the rest of the emulator).

September 2015

2015-09-27: Coding, Emulator

Solved serialisation bugs, implemented much more functionality. The DFP can now read and write to memory and I/O.

2015-09-19: Coding, Emulator

DFP firmware now has access to most of the Emulated CFT. Some operations still can't be performed. A couple of serialisation bugs have appeared.

2015-09-10: Coding, Emulator

Working on adding the full DFP firmware into the emulator.

2015-09-04: Coding, Emulator

Working on adding the full DFP firmware into the emulator.

2015-09-03: Coding, Emulator

DFP Firmware now running on the emulator! Still mostly throws ‘NOT IMPLEMENTED’ messages and has no access to the emulated machine.

2015-09-02: Coding, Emulator

Working on adding the full DFP firmware into the emulator.

August 2015

2015-08-31: Coding, Emulator

Working on adding the full DFP firmware into the emulator.

2015-08-30: Coding, Emulator

Working on adding the full DFP firmware into the emulator. DFP firmware now compiling as library and linking against the emulator.

2015-08-29: Coding, Emulator

Working on adding the full DFP firmware into the emulator.

2015-08-01: Coding, Emulator

Working on adding the full DFP firmware into the emulator.

July 2015

2015-07-30: Bugs, Construction, Hardware, Processor Board 1

Produced CAM files for PB1, ready to reprint PCB.

June 2015

2015-06-15: Bugs, Construction, Hardware, Processor Board 1

Progress with the revision G PB1 board.

May 2015

2015-05-04: Bugs, Construction, Hardware, Processor Board 1

Updated the rev G PB1 schematic with the newest write circuitry bug fix (the added NOT gate so the circuit floats when HALT# is asserted, not the other way round).

2015-05-03: Documentation, Website

Updates the CFT microcode-level emmulator to use the newest DFP addresses, so it can use the newest Assembly include files.

2015-05-03: Coding, Software, ROM

Now tha the Javascrpit emulator is so much faster, I've added short welcome messages to most of the sample ROM's programs, including a boot-up message. The ROM now showcases the Assembler (and instruction set) pretty well: it has macros, scopes, subroutines, extended instructions, the works. I've refactored the ROM to get rid of old cruft, cleaned and reformatted up the source, and annotated everything with comments. The ROM is now published on the web anyway.

2015-05-01: Bugs, Construction, Hardware, Processor Board 1

Patched PB1 write strobe circuitry. One last bug remaining: the circuit should tri-state when HALT# is de-asserted. It's currently doing the reverse (a NOT gate is needed).

2015-05-01: Bugs, Testing, Debugging Front Panel

Patched the DFP so it doesn't use open drain drivers for MEM#, IO#, R# and W#. One minor hardware patch needed: snip the ABOE# signal to board 2. This will permanently disable NOPROC mode, and the current AB-OE# signal will then be renamed to BUSEN#. Obviously, this will require changes to the DFP firmware. On the up side, with NOPROC mode removed, the firmware will be smaller.

April 2015

2015-04-06: Documentation, CFT Book

Worked on the documentation. It dawns on me that I should probably port the documentation to HTML, XML or somesuch instead and use LaTeX for the diagrams. I can then re-import it into LaTeX to generate PDFs — when/if I decide to do so. These days, HTML can be have more semantics than TeX!

2015-04-05: Documentation, CFT Book

Added some content to the CFT Book (processor description). Corrected a few errors. Re-added the Javascript emulator with new text, including the ROM source code. Published the documentation on the live website.

2015-04-04: Documentation, CFT Book

More work on the CFT Book conversion, as well as the CFT section on the BedroomLAN site.

2015-04-03: Documentation, CFT Book

More work on the CFT Book conversion, as well as the CFT section on the BedroomLAN site.

2015-04-02: Documentation, CFT Book

More work on the CFT Book conversion, as well as the CFT section on the BedroomLAN site.

2015-04-01: Documentation, CFT Book

First drafts of The CFT Book (at least the non-empty chapters) are now online. Hyperlinks are stripped out of the documents and there's still need for plenty of CSS styling, but at least the information is online again.

March 2015

2015-03-30: Documentation, CFT Book

Much progress with the documentation converter. For now, it's generating a single, huge HTML file with proper markup including SVG images (but currently not maths). Once cross-chapter links are converted and a stylesheet is written, it will be possible to publish an early version of the documentation.

2015-03-29: Documentation, CFT Book

Additional work on the documentation converter. Puzzling out TeX Math to SVG conversion.

2015-03-10: Documentation, CFT Book

Started work on converting the CFT Book (HTML version) to Jinja 2 HTML suitable for the BedroomLAN site.

November 2014

2014-11-07: Bugs, Testing, Debugging Front Panel

Rewired control bus to fix issues with the DFP.

October 2014

2014-10-05: Coding, Software, ROM

Completed the PS/2 keyboard handler. Keyboard events are now read and inserted into the event queue of the current process.

2014-10-03: Bugs, Testing, Debugging Front Panel

After not having been touched for a couple of weeks, the CFT hardware is failing diagnostics for the AC (IBUS trouble, possibly a short) and PC (it never changes, possibly WPC connection broken or shorted). DFP Board 2 is almost certainly to blame for this.

September 2014

2014-09-29: Coding, Software, ROM

Added the KBD Interrupt handler. The OS can now read from a PS/2 keyboard.

2014-09-28: Coding, Software, ROM

Worked on the VDU/KBD driver. The driver has extremely rudimentary tty support. It can output characters (so the initial text-mode banner is visible) but not yet scroll, etc. Code cleanups.

2014-09-27: Coding, Software, ROM

Work on the VDU driver for the OS.

2014-09-27: Documentation, CFT Book

Documented the new interrupt state machine, including state diagrams and waveforms.

2014-09-26: Design, Hardware, Processor Board 1

Reworked the Rev F PB1 schematics and PCB to include the fifth state in the interrupt state machine.

2014-09-26: Coding, Software, ROM

Work on the VDU driver for the OS.

2014-09-20: Setbacks, Coding, Software, ROM

Interrupt driven, FIFO-based I/O is going well, but I have struck my worst-case scenario: an interrupt being signalled between the SEI and RTI instructions, which means two things: (a) the ISR will have to re-entrant (or have a return stack), and (b) interrupts are coming in faster than the ISR can handle, even with just a TTY.

2014-09-19: Coding, Software, ROM

Work on interrupt-driven TTY I/O.

2014-09-18: Coding, Software, ROM

Work on FIFOs and interrupt-driven TTY I/O.

2014-09-13: Coding, Software, ROM

Work on the ROM. Modulo some more refactoring, I'm ready to start adding the ROM Forth interpreter back to the mix. The ROM Forth dictionary will be pared down to the essentials, so the interpreter, compiler and essential features can fit in 8kW. Forth 83 support can be added later, which will allow another 8kW for the language. Then, another 8kW should add support for most of the hardware.

2014-09-12: Coding, Emulator

Finished the memory inspection code in the emulator and used it to track down an issue with the TTY driver code.

2014-09-12: Design, Hardware, Processor Board 1

Since the DFP is working well with the processor, and it's the only bus-mastering device, and since the PB1 has so many bugs, I've all but decided to give up on tri-stating the W# signal on it. The design will include it, but PB1 doesn't need it for the computer to work. W# can be driven full-time with no ill effects: the DFP simply drives the processor's internal WEN# signal which generates W# pulses. This should be fine fow now. Later, if I feel like it, I'll have Revision F of the PB1 re-printed and construct a new one with all the corrections.

This is a design decision motivated by laziness too: hand-soldering Kynar wire onto SOT-23 devices with a soldering iron (and solder) meant for DIP chips isn't easy.

2014-09-12: Coding, Software, ROM

Work on the ROM.

2014-09-11: Coding, Software, ROM

Work on the ROM.

2014-09-11: Coding, Emulator

Fixed numerous bugs with the emulator. Added a memory inspection feature.

2014-09-11: Coding, Cross-Assembler

Fixed bug with error reporting.

2014-09-06: Testing, Hardware

Created, rendered and uploaded video of the CFT running its first program. Posted on Google Plus and Facebook.

2014-09-05: Testing, Processor Board 1

I tracked down garbled register writes (via the DFP) to signals not being deasserted with HALT# asserted, and then to just MEM# and R# staying asserted. These signals are routed to the CFT busplane, and have bus-hold circuits, so when the Microcode Store ROMs stop driving them, the bus hold keeps them at their previous state. I fixed this by pulling up MEM#, IO#, R# and W# and adjusting the schematics.

2014-09-05: Bugs, Testing, Debugging Front Panel

The w(rite) command seems to leave the MEM# and R# signals at an indeterminate state (~1.6V). The fill command doesn't do this though. After a fresh power cycle, the DFP can perform reads from the SRAM, fill memory with specific values and read them back. After a single w command, this is compromised.

2014-09-05: Bugs, Testing, Processor Board 2

At clock frequencies over 0.614 MHz (15% of the intended clock rate), incrementing the AC fails. The second counter seemingly wraps around at 127 or 255. The latter is clearly a carry propagation issue, but I'm not sure what the former is. The AC carry chain works fine at 0.614 MHz, and the PC carry chain works fine at 4 MHz.

2014-09-05: Bugs, Testing, Processor Board 1

Write signal generation works, but once the signal is released it slowly curves back to +5V over the course of around 400 ns. This looks like the normal waveform shape for an open drain circuit, just horrendously elongated, possibly because of the parasitic capacitance of the backplane. I need a totem-pole driver for W#, so it's back to the original plan to use a 74'1G125 single tri-state buffer.

2014-09-05: Milestone

The CFT processor has executed its first two programs, designed to operate without an ALU (which isn't yet installed). Both programs incremented the AC in tight loops (one also sent data to the front panel debugging interface).

2014-09-04: Bugs, Testing, Processor Board 1

The Control Bus ribbon cable needs to be mechanically stronger. Minor movements of cards can unplug it partially, causing various sorts of grief.

2014-09-04: Bugs, Testing, Debugging Front Panel

Some of the control signals appearing on the front panel are mis-read by the input shift registers, breaking microcode disassembly. INCPC# is currently an issue.

2014-09-01: Coding, Software, ROM

Minor refactoring of the ROMs.

August 2014

2014-08-30: Coding, Software, ROM

Added assembler definitions for 16550 UARTs. I always forget they're quite complex devices!

2014-08-29: Bugs, Testing, Processor Board 0

The RUNIT1 issue seems to be a short. The signal goes up to ~2.4V, but the PB0 tests out okay (10kΩ between the µ00 ROM pin and GND, >1MΩ between the pin and Vcc). The issue must be somewhere else, then (RUNIT1 is also on the control bus).

Update: tracked the issue to a tiny solder bridge on DFP Board 2, the usual culprit for shoddy construction. Shockingly, with the RUNIT field operational, the computer is now working and executing a nonsensical program, including talking to the DFP itself! (PRINTx instructions being logged).

2014-08-29: Bugs, Testing, Debugging Front Panel

Some DFP I/O instructions cause the DFP to crash, and the watchdog causes a reset. This one is a bit premature, of course.

2014-08-28: Bugs, Testing, Processor Board 0

If the Microcode Store is in a state when IR is being written, even with the processor halted, you can't modify the IR via the switches or debug UI. This shouldn't be the case, all the units should be idle with the processor halted, and the microcode lights certainly indicate just this (all off).

2014-08-28: Bugs, Testing, Debugging Front Panel

When the CFT starts halted, (RAM/ROM switch set to RAM), the DFP doesn't give the processor enough clock ticks to de-assert RSTHOLD#. This should be part of the reset function (let the clock run and ensure the RESETTING state has cleared by looping until the WAIT# input is 1).

2014-08-27: Bugs, Testing, Processor Board 1

Signal IBUS10 does not appear to be held properly, or is shorted to ground somewhere. When the DFP writes FFFF to the IBUS and then stops driving, the IBUS changes to FBFF. Likewise, 0400 flickers between 0400 and 0000, even while being supposedly driven. Perhaps DFP Board 2 isn't driving that bit properly. This doesn't always happen, though, and all register diagnostics pass for PC, AC and IR.

2014-08-27: Bugs, Testing, Processor Board 2

Sometimes, the AC diagnostics fail with the lower nybble of the AC seemingly stuck to 0. (i.e. writing FFFF, but reading back FFF0).

2014-08-27: Bugs, Testing, Debugging Front Panel

The DFP ustep command can step multiple times (even if single stepping). Sometimes, the step ends with some lights illuminated, other times the lights are idled (and all lights on the front panel are off).

2014-08-26: Coding, Software, ROM

Coded DFP TTY driver as a proof of concept. Added NULL (sentinel) driver. Added driver abstraction and basic system call support. You can now output characters to abstract terminal devices.

2014-08-25: Coding, Software, ROM

ROM development and fixes. Refactoring old asm directory, and started merging code into a new ROM subproject. Worked on the basic OS calls.

2014-08-24: Coding, Emulator

Fixed bugs with the IRC in the C emulator. Added support for the DFP terminal using code taken directly from the DFP firmware. Lovely how code can be shared between firmware and emulator!

2014-08-24: Coding, Software, ROM

Minor ROM development and fixes. Started work on refactoring the Forth interpreter to fit the new memory layout, OS primitives and Assembler improvements.

2014-08-23: Bugs, Testing, Debugging Front Panel

WEN# was pulled up (by the PB0) and down (by the DFP) simultaneously. Removed the DFP resistor and good riddance. I keep finding these!

The PC4 pin on PB2's IC12 counter was connected to +5V via a tiny solder bridge under the chip (too much solder paste, which is what you get when you solder with paste and no stencil). I clipped the pin, reheated the space under the chip very carefully, verified the bridge had sublimated and absorbed by pads, then re-connected the pin to the pad with a very short length of wire.

Bus Writes via the processor don't seem to work. Bus reads may also be non-functional but it's difficult to test without bus writes (memory seems to initialise to &FFFF).

2014-08-19: Coding, Software, ROM

Added memory allocation functionality to the ROM. It only has bank granularity for now. Much closer to re-incorporating the Forth interpreter in the new OS framework.

2014-08-18: Coding, Software, ROM

Added entry/exit conventions to the macro definitions. Minor work on the ROM.

2014-08-15: Testing, Firmware, Debugging Front Panel

Fixed halting bug.

2014-08-15: Bugs, Testing, Debugging Front Panel

Loading the IR from the SR fails. This could be a firmware bug. The IR0 and IR1 (or IBUS0 and IBUS1) signals are swapped somewhere. Setting the SR for 0002 makes the IR 0001 and vice versa. Tracked down to swapped IBUS wires on the PB2. No biggie.

Going through the test script for the DFP, I discovered yet another signal that was pulled up and down simultaneously: WAIT#. I'm removing the pull-down.

And more of the same: some unit is still driving the IBUS with the machine halted. It's not DFP board 2, because I'm getting mismatched values when writing to the IBUS from it. PB1 doesn't use the IBUS, so the culprit must be on PB1, and specifically the AGL, Data Bus Transceiver, or numerous shorts. Update: fixed quite early. The real culprit was the control bus ribbon cable not being plugged into PB0.

Yet another bug: when microstepping, the last step of a microprogram is skipped because END# seems to take effect immediately. This is probably because the µPC is reset asynchronously but incremented synchronously. Update: fixed when the PB0 ribbon cable was reconnected.

The microcode control vector isn't read correctly on the DFP serial interface, but displays correctly on the panel light.

The computer seems to be selecting the ROM bank on the MEM board regardless of the setting of the RAM/ROM switch on the front panel.

The PC on PB2 does not increment correctly. Bit 4 is stuck on, and the PC counts between &0010-&001F inclusive. Carry aggregation issue? It could also be an issue with the front-panel buffers.

2014-08-15: Design, Hardware, Debugging Front Panel

The ‘reset’ light lights when the RSTHOLD# signal is asserted (processor's reset state). Since resetting always runs at full speed, it may be nice to turn this light on during RESET# or RSTHOLD# assertion. A wired AND gate will do for this, and there's plenty of space available for it.

2014-08-13: Bugs, Testing, Hardware, Debugging Front Panel

The microcode store now works (seemingly). Various apparent issues seem to be stemming from the missing PC and AR registers. Perhaps it's time to start testing PB2.

2014-08-13: Bugs, Testing, Firmware, Debugging Front Panel

When switching from Creep to Slow mode via the front switch, it often takes a while for the change to take place. This is likely a firmware bug, since the same command from a controlling computer works fine.

2014-08-04: Setbacks, Bugs, Testing, Hardware, Debugging Front Panel

It turns out that both control signals to the IR are wrong. when the IR flip flops were replaced with latches, the WIR# active low signal should have been inverted ('573 have an active high latch enable pin). So the IR only updates its value when it's not supposed to, and it never outputs a value. An '1G04 inverter is being used to fix this.

Additionally, and this is a good thing, during the patching I discovered the WIR# signal didn't in fact reach both latches. This looks like a PCB defect, and may mean there are others.

2014-08-04: Testing, Hardware, Processor Board 1

IR issues fixed. The IR now displays as &FFFF without memory installed, and is routed to the µADDR vector correctly. The WIR# signal isn't generated yet though, because there's still a short or other issue with the RUNIT field in the microcode.

2014-08-03: Coding, Software, ROM

Ported stack macros from ROM Forth to the new architecture.

2014-08-03: Tools

Fixed macro argument expansion bug.

2014-08-02: Testing, Hardware

Created, rendered and uploaded video of DFP, PB0 and PB1 testing to YouTube. Posted on Google Plus and Facebook.

2014-08-01: Testing, Hardware, Debugging Front Panel

Removed the stupidly connected LEDs from the RESET# circuitry, and the CFT finally works. The µPC is enabled and counts up on the front panel. Updated testing plan with the workings of DFP. Fixed issue with Fetch/Exec decoder (it was working fine, the DIP switches weren't set properly). Fixed issue with AB0 stuck on (the joint between the output and the pull-ups had broken, so the line was never driven down).

2014-08-01: Bugs, Testing, Hardware, Debugging Front Panel

The Fetch/Exec decoder lights don't currently work. Bit 0 of the Address Bus is stuck on (seems to be DFP Board 2's fault). Potential short between RUNIT1 and RUNIT2 on PB0. Lights miswired: the microcode vector goes END, WEN, R, IO, MEM. The panel lights go END, W, R, MEM, IO (this should probably be fixed by rewiring on DFP board 1 and changing the labels on the front panel design).

2014-08-01: Bugs, Testing, Hardware, Processor Board 1

A gorgeous, annoying bug: The part used for the Instruction Register was changed from a flip flop with clock and reset to a latch with latch enable and output enable. The location of the reset (flip-flop) and output enable (latch) signals were the same on both schematic and board, and both received the same signal: RESET#. This work with a flip-flop (resetting the IR), but fails on the latch (the IR only drives during reset, not always). The PB1 will thus have to receive its fourth patch.

2014-08-01: Bugs, Testing, Hardware

Potential LED wiring issue. RUNIT1 bit seems wrong. Bit(s) flipped or shorted somewhere?

July 2014

2014-07-31: Coding, Software, ROM

Added retro modes. When the computer is booted with the Switch Register holding a BCD-encoded year in the 20th Century (19xx), the computer will only enable some subsystems to emulate a typical computer from that year. Code various other cleanups and added new useful macros.

2014-07-30: Coding, Software, ROM

Added code to decode VDU format images and blit them to the VDU. Wrote various additional parts of the boot loader code.

2014-07-29: Tools

Created a small tool to perform minimal quantisation on images and convert them to VDU format. The img2vdu tool already ostensibly does this, but its output is currently flawed. This minimal version will be integrated with it eventually.

2014-07-29: Coding, Software, ROM

Generated the CFT logo in VDU format, suitable for assembling as part of the ROM and blitting to the VDU.

2014-07-28: Coding, Software, ROM

Added vdu.asm include file with assembly-level descriptions of the VDU version 5 registers.

2014-07-28: Coding, Emulator

Implented some more of the VDU for the JS emulator.

2014-07-28: Documentation, CFT Book

Fixed minor issues with the VDU documentation.

2014-07-27: Coding, Software, ROM

Some work on the early boot ROM. Boot banner now prints out available memory.

2014-07-27: Tools

Working on implementing banks on the CFT Assembler.

2014-07-27: Coding, Emulator

Implemented much of the VDU in the JS emulator.

2014-07-26: Design, Hardware, Processor Board 1

Stepped PB1 to Revision F, modified schematics and routed board (datecode 1430).

2014-07-25: Testing, Hardware, Debugging Front Panel

Implemented WS state machine fixes. Located more logic errors with the state machine, and also fixed those. Again, only rewiring was necessary. A serious firmware error was also fixed, and now the processor is reset properly and goes through a perfectly valid reset sequence: the microcode store asserts the right signals, and those signals drive the processor and bus.

2014-07-25: Bugs, Testing, Hardware, Debugging Front Panel

The PB1 LEDs lack transistors, so they lower the voltage on their logic lines. This was really stupid. The proposal is to remove the LEDs or hack the board to add the transistors (luckily there's enough space).

2014-07-24: Testing, Hardware, Debugging Front Panel

The WS state machine errors have been located and fixed. Luckily, only rewiring of a few signals was needed. No IC or passive component changes.

2014-07-23: Bugs, Testing, Hardware, Debugging Front Panel

There seems to be an issue with the WS# signal. In this condition, the contents of the IR on the front panel ‘fade away’ (either literally fade away flickering, or lights are extinguished one by one) as if the IBUS is floating (which it shouldn't be, there are bus hold ICs in place), or WIR# is triggering.

2014-07-23: Setbacks, Bugs, Testing, Hardware, Debugging Front Panel

The WS# issue had two parts: one, many of the WS state machine's pins weren't pulled up or down accordingly. Fixing this resolved the instability of the flip flops. Two, there appear to be serious logic errors in the WS state machine design.

2014-07-19: Testing, Hardware, Debugging Front Panel

Last night's problem traced to POWEROK being 3.3V. Temporarily wired POWEROK to +5V and reset (including the RSTHOLD# timing) is working cleanly now.

2014-07-19: Bugs, Testing, Hardware, Debugging Front Panel

The reset sequence fails because of what looks like a software bug. A manually coded RESET sequence (without the firmware fully initialising) seems to work fine. Also, there may be an issue with HALT#.

2014-07-18: Construction, Hardware, Processor Board 1

Patched PB1 so that W# is now an open drain signal. When asserted, it's driven by an open drain NAND gate from the Q (active high) output of write strobe state machine. When de-asserted, the line is at high impedance and pulled up by a 4.7kΩ resistor. Bus Hold and a 30Ω impedance matching resistor take care of signal conditioning.

2014-07-18: Testing, Hardware

Drew up testing plan for each individual unit of the processor.

2014-07-18: Bugs, Testing, Hardware, Debugging Front Panel

The Clock multiplexer (IC40) on board 1 of the DFP is receiving a garbled waveform from the MCU for FPUSTEP-IN. Possible short-circuit? FPCLKEN-IN seems to be okay. There also seems to be a lot of ringing on the longer wires, and IC40 is quite far from the MCU.

2014-07-17: Design, Hardware, Processor Board 1

Redid the PB1 W# tristate patch to use a open-drain NAND gate rather than a tri-state buffer. This will be much faster (and I have single OD NAND gates in stock as well).

2014-07-17: Design, Software, Microcode

Added EXTSKIP# support to the IOT instruction. I forgot about that in previous versions. Microcode revision is now 6c.

2014-07-16: Testing, Hardware

Drew up spreadsheet of all cross-board processor signals and their conditioning. This will be useful in running boards one by one.

2014-07-14: Documentation, CFT Book

Added a little bit to the DFP documentation.

June 2014

2014-06-13: Testing, Hardware, Debugging Front Panel

Fixed numerous bugs on both DFP boards. All lights are now working properly.

2014-06-13: Bugs, Testing, Hardware, Debugging Front Panel

The Data Bus enable MUX on DFP Board 2 is not putting out correct values. It may have a dry joint or short, though it seems like all pins test correctly. The theory is correct and the chip works (multiple chips tried), so something else is wrong.

2014-06-12: Bugs, Testing, Hardware, Debugging Front Panel

The POWEROK signal from modern ATX power supplies uses 3.3V, not 5V. This will eventually have to be level-shifted, but the machine will likely work without it: POWEROK is only used for brownout detection, and the Atmega can detect such cases and hold down RESET#. The DFP also boots with RESET# asserted, until the MCU passes diagnostics, which is the same as waiting for the power supply to assert POWEROK.

2014-06-12: Setbacks, Bugs, Testing, Hardware, Debugging Front Panel

The entire low order 8 bits of DR have been reversed! They are reversed on Processor Board 1 to simplify routing, and the DFP wiring is wrong. All eight signals will have to be flipped around on Board 1 of the DFP.

2014-06-12: Testing, Hardware, Debugging Front Panel

Verified most of the front panel lights.

2014-06-07: Bugs, Testing, Hardware, Debugging Front Panel

The programmable bus pull-up goes through a diode driven by an inverter (so it's at H or Z, never L). The diode produces a voltage of around 4V, which is quite marginal. Under heavy load and/or fast switching, some active-low bus signals can activate inadvertently. Need to replace the inverter and diode with a '541. It can source 35mA, and provides the same functionality. A capacitor could also help.

2014-06-06: Testing, Hardware, Debugging Front Panel

Inputs from AB0–AB3 on Board 2 were reversed! Also, AB0 was shorted and producing random values (which appeared as AB3 because of the reversal). After fixing these two issues, the Address Bus diagnostics work fully. Data Bus I/O also works, but the DB can't be tri-stated until the few remaining IC sockets on board 1 are populated. Until then, the Data Bus enable circuitry thinks the CFT is reading from the DFP and drives the Data Bus with data.

2014-06-06: Bugs, Testing, Hardware, Debugging Front Panel

Using the front panel switches to set the address in standalone mode doesn't work because the PC sanity checks fail (value written is not read back correctly — naturally, because there's no PC in standalone mode).

2014-06-05: Testing, Hardware, Debugging Front Panel

Fixed memory cycle bug.

2014-06-05: Bugs, Testing, Hardware, Debugging Front Panel

The least significant Address Bus nybble (AB0–AB3) seems to have some issue. Values driven are not read back correctly, and DFP bus diagnostics fail. Also, the Data Bus can't be tristated.

2014-06-03: Coding, Hardware, Debugging Front Panel

Early version of a PC-side DFP communications tool (written in Python 3.4).

2014-06-03: Testing, Hardware, Debugging Front Panel

Fixed several bugs with the output shift registers (mainly missing wires). The DFP now correctly updates the OR and asserts various bus signals (some incorrectly).

2014-06-03: Bugs, Testing, Hardware, Debugging Front Panel

There are some issues with the bus writes. Some bits of the control bus (namely IC35, the last SR in the chain) seem to be linked: FPRUN/FPSTOP with MEM# or IO#. This is probably a software error.

2014-06-03: Bugs, Testing, Hardware, Debugging Front Panel

Some command pulses may be too short. Symptom: some reads are incorrect (e.g. 0100 becomes 0110), like the shift registers failed to shift the data between samples. This is plausible since the '165 SRs shift out MSB-first.

2014-06-01: Coding, Hardware, Debugging Front Panel

Early version of a PC-side DFP communications tool (written in Python 3.4).

May 2014

2014-05-28: Coding, Hardware, Debugging Front Panel, Firmware

Made the swtest command echo the value of the SR to the OR to facilitate testing the lights (and output shift registers, which are currently not working).

2014-05-28: Bugs, Testing, Hardware, Debugging Front Panel

Drew up testing plan for front panel lights.

2014-05-16: Setbacks, Testing, Hardware, Debugging Front Panel

Broke some cables near the connectors to light assembly 3. I'll have to either find the breaks and patch them somehow, or recrimp an entire new flat cable.

2014-05-16: Bugs, Testing, Hardware, Debugging Front Panel

All the light modules were installed upside down. This will necessitate updating the drilling patterns for the light assembly mounting plate.

2014-05-16: Bugs, Testing, Hardware, Debugging Front Panel

IR11 isn't being pulled up (but is connected).

2014-05-16: Bugs, Testing, Hardware, Debugging Front Panel

The OR resets to FFFF but the DFP 'or' command doesn't update it. This could be a software bug, or an issue with the shift register clocks.

2014-05-10: Bugs, Testing, Hardware, Debugging Front Panel

The R signal was both pulled up and down, ending up at 2.5V and confusing one of the shift registers of the virtual front panel. The same was true of another two signals.

2014-05-09: Testing, Hardware, Debugging Front Panel

Fixed the lights off switch. Many of the grounding wires from the switch assembly were inadvertently connected to the lights on signal (which connects to ground when lights are on, enabling front panel LEDs). This included the power switch: turning lights off would disconnect ground, deasserting the power on signal and turning the PSU off.

2014-05-09: Testing, Hardware, Debugging Front Panel

Second testing session of the DFP. Both boards are plugged into the backplane and communicating. The MCU, both 74HC259 control chips and their inverters, as well as ten input shift registers are populated and working. Current draw is approximately 50 mA.

2014-05-09: Bugs, Testing, Hardware, Debugging Front Panel

Roughly half of the switches are pulled down instead of up (16 signals in all). It was more convenient to do that with the 74HC165 shift registers because half of the pins are closer to the ground rail. The fix is less pleasing to the eye, but it works now.

2014-05-09: Bugs, Testing, Hardware, Debugging Front Panel

The switch register (as sampled by the MCU) appears to have its bits reversed (switch 0 is bit 15). It's a nomenclature error, since switches were originally numbered in DEC style (the left most switch is SR0, but bit 15 of the SR). It may be a switch assembly wiring issue, but it was trivial to fix in software.

2014-05-09: Bugs, Testing, Hardware, Debugging Front Panel

I inadvertently swapped the signals for the Set Address and Set Accumulator switches on the switch break-out board.

2014-05-08: Setbacks, Testing, Hardware, Debugging Front Panel

All of the 40-pin sockets on board 2 are upside down! It's the only way to do it, since the sockets on the other boards are right-angled ones. Unfortunately, this makes the ribbon cables a lot less tidy, but it's not impossible to connect. The DFP board 1 and board 2 connection was going to be diagonal anyway, since the sockets don't align.

2014-05-08: Construction, Hardware, Debugging Front Panel

Made ‘round’ flat cable assemblies which are more flexible and take up less space.

2014-05-08: Setbacks, Testing, Hardware, Debugging Front Panel

The lights off switch apparently shorts the front panel. No harm done, the ATX power supply is protected against shorts.

2014-05-07: Construction, Hardware, Debugging Front Panel

Seventeenth construction session for Board 1. The board has now been fully wired, with the exception of the custom peripheral lights, which will be wired on demand.

2014-05-07: Testing, Hardware, Debugging Front Panel

Sounded out most of the sensitive connections and removed some duplicate pull-up/donw resistors.

2014-05-03: Construction, Hardware, Case

Wired power supply harness for backplane and DFP. This one is meant for testing. The final one will be a length appropriate for the layout of the case.

2014-05-03: Construction, Hardware, Debugging Front Panel

Sixteenth construction session for Board 1. The MCU is now fully wired and can be tested.

2014-05-02: Construction, Hardware, Case

Experimented with hardware for fixing backplane onto case.

2014-05-02: Construction, Hardware, Debugging Front Panel

Fifteenth construction session for Board 1. Wiring left-over signals, cleaning up, fixing errors and installing 0805 impedance matching resistors, pull-ups and pull-downs. In some cases, replacing through-hole passives with 0805 parts.

April 2014

2014-04-29: Orders

Additional passives arrived.

2014-04-25: Changelog, Documentation, Progress

Worked on Drupal side of the Changelog publishing mechanism.

2014-04-24: Changelog, Documentation, Progress

Worked on Drupal side of the Changelog publishing mechanism.

2014-04-24: Documentation, Website, Documentation, CFT Book

Preparing CFT book for publication on the web (using Drupal's Feed module to import HTML as Drupal nodes).

2014-04-23: Changelog, Documentation, Progress

Created conversion/import toolchain to publish the Changelog as a progress log.

March 2014

2014-03-28: Construction, Hardware, Debugging Front Panel

Fourteenth construction session for Board 1. Rewired the MCU and started adding impedance-matching resistors to most of its outputs. Wired shift register control signals, clocks and enables. Fully connected and tested power and ground. Board 1 is now almost ready to be tested. The remaining signals connect to the right bank of lights, and they will be connected as needed since appropriate headers will need to be made for them.

2014-03-28: Orders

Ordered more 30Ω 0805 resistors.

2014-03-24: Design, Hardware, Case

More work on the case design.

2014-03-24: Orders

Ordered hardware needed to fix the backplane in place (and provide power to it).

2014-03-23: Design, Hardware, Case

More work on the case design. Placed the backplane and fixed design issues.

2014-03-22: Design, Hardware, Case

More work on the case design, with emphasis on the front panel light and switch assemblies.

2014-03-21: Design, Hardware, Case

Drafted key lock component in SketchUp.

2014-03-21: Construction, Hardware, Debugging Front Panel

Fourteenth construction session for Board 1. Wired the MFD outputs (48 wires).

2014-03-20: Design, Hardware, Case

Designing a case in SketchUp to ensure all the assemblies match properly. Completed the switch assembly and drafted the backplane.

2014-03-19: Design, Hardware, Case

Designing a case in SketchUp to ensure all the assemblies match properly. Draw the switch assembly and various additional components.

2014-03-18: Design, Hardware, Case

Designing a case in SketchUp to ensure all the assemblies match properly. Drafting the front panel light assembly.

2014-03-17: Design, Hardware, Case

Designing a case in SketchUp to ensure all the assemblies match properly.

2014-03-13: Construction, Hardware, Debugging Front Panel

Thirteenth construction session for Board 1. Wired the PC (thus completing the PB2 front panel connections) and various miscellaneous signals, including passive components. Corrected more errors.

2014-03-12: Construction, Hardware, Debugging Front Panel

Twelfth construction session for Board 1. Connected front panel common anodes. The front panel light assembly could now (in theory) be used!

2014-03-06: Construction, Hardware, Debugging Front Panel

Eleventh construction session for Board 1. Wired the remaining P5 and corrected various wiring errors. (388 signals total).

2014-03-05: Construction, Hardware, Debugging Front Panel

Tenth construction session for Board 1. Wired the remaining P4 (the PB0 front panel connector) and debugged issues. Currently wiring connector P5 (the PB1 front panel connector, carrying the IR and a few other signals).

2014-03-03: Coding, Emulator

Synchronised the C emulator with the current I/O map. Various minor issues fixed. The C emulator now runs the alpha bootloader ROM.

2014-03-02: Coding, Software, ROM

Work on boot loader code.

2014-03-02: Coding, Website

Some improvements to the JS emulator.

2014-03-01: Coding, Software, ROM

Wrote MBU and MEM detection algorithms.

2014-03-01: Tools

Added .scope/.endscope directives to allow scoped labels (this internally reduces to anonymous namespaces). Added .longstring/.endstring directives to facilitate packing of multi-line .strp directives.

February 2014

2014-02-28: Coding, Software, ROM

Refactoring assembler include files to use namespaces and the new, more mature coding style.

2014-02-28: Tools

Fixed issues with the assembler getting confused with forward .equ/.reg definitions.

2014-02-26: Tools

Version 2.2 of the CFT Assembler. This version introduces namespaces.

2014-02-26: Miscellaneous

Created emacs major mode for editing CFT Assembler files in the proper style.

2014-02-25: Coding, Website

Work on the JS emulator continues. A release candidate is now ready, including an updated test ROM.

2014-02-25: Tools

Version 2.1 of the CFT Assembler. This version introduces include paths.

2014-02-25: Coding, Hardware, Debugging Front Panel, Firmware

Improved the DFP firmware's interrupt handling. Standardised on flag values.

2014-02-25: Coding, Software, ROM

Started coding early parts of the ROM.

2014-02-24: Coding, Website

Processor, UCB and MBU emulation is now in place.

2014-02-22: Coding, Website

Started work on an instruction-level CFT emulato, which will become version 2.

2014-02-18: Documentation, Website

Updated JavaScript CFT microcode-level simulator for the newest panel layout and colours.

2014-02-18: Documentation

Created list of CFT assemblies, wiring and parts.

2014-02-17: Orders

Mouser order (bypass capacitors, pull-up/down resistors, Kynar® wire, NKK® key switches) arrived.

2014-02-14: Testing, Coding, Hardware, Debugging Front Panel, Firmware

Numerous small fixes to the DFP firmware.

2014-02-11: Construction, Hardware, Debugging Front Panel

Ninth construction session for Board 1. Wiring the remaining P4 (the PB0 front panel connector). Ran out of Kynar® wire and the replacement turned out not to be Kynar (not enough heat resistance).

2014-02-11: Orders

Ordered more bypass capacitors, pull-up/down resistors, Kynar® wire, and also some better-quality NKK key switches for the front panel.

2014-02-10: Testing, Coding, Hardware, Debugging Front Panel, Firmware

Implemented first DFP board self-diagnostics.

2014-02-10: Design, Hardware, Debugging Front Panel

Made two slight changes to the hardware for more reliable diagnostics.

2014-02-09: Testing, Coding, Hardware, Debugging Front Panel, Firmware

Built more of the test/simulation framework for the DFP. Discovered and fixed some bugs.

2014-02-08: Testing, Coding, Hardware, Debugging Front Panel, Firmware

Built more of the test/simulation framework for the DFP.

2014-02-07: Construction, Hardware, Debugging Front Panel

Eighth construction session for Board 1. Completed wiring of switch input socket.

2014-02-02: Design, Hardware, Video Display Board

Minor changes to the VDU board design.

2014-02-01: Common, CFT Book

Working on HTML version of documentation.

January 2014

2014-01-27: Common, CFT Book

Working on HTML version of documentation: build framework, macro set, style, content. Created pygments lexer for Microcode assembler, added scripts to generate images of PCBs out of Gerber files.

2014-01-24: Common, CFT Book

Working on HTML version of documentation: build framework, macro set, style, content.

2014-01-22: Common, CFT Book

Working on HTML version of documentation: interactive mode demonstration widget for VDU documentation.

2014-01-21: Common, CFT Book

Working on HTML version of documentation: build framework, macro set, style, content.

2014-01-20: Design, Hardware, Video Display Board

Minor changes to the VDU board. Added an extender port for optional VDU daughterboards (e.g. for a sprite engine).

2014-01-20: Common, CFT Book

Working on HTML version of documentation: build framework, macro set, style, content.

2014-01-17: Common, CFT Book

Working on HTML version of documentation.

2014-01-15: Common, CFT Book

Drew new version of the datapath.

2014-01-15: Construction, Hardware, Debugging Front Panel

Seventh construction session for Board 1. Wired AEXT lights, AC register, plus a few miscellaneous signals.

2014-01-14: Common, CFT Book

Second attempt to produce a hybrid PDF/HTML version of the CFT book. This one is coming along better than previous ones. It uses TeX4ht with a number of hacks to sidestep issues like colour and Unicode support and converts figures, timing diagrams and other ‘difficult’ objects into bitmaps.

2014-01-11: Construction, Hardware, Debugging Front Panel

Sixth construction session for Board 1.

2014-01-10: Construction, Hardware, Debugging Front Panel

Fifth construction session for Board 1. Added approximately 90 pull-up/down resistors to protect CMOS input stages against operation with floating inputs (e.g. missing processor).

2014-01-09: Construction, Hardware, Debugging Front Panel

Fourth construction session for Board 1. Slow work due to the complex cable routing requirements (376 signals in total, plus bus rails).

2014-01-08: Testing, Coding, Hardware, Programmer's Front Panel, Firmware

Debugging DFP with the help of the simavr framework. Fixed bus pull-ups.

2014-01-08: Construction, Hardware, Debugging Front Panel

Third construction session for Board 1. Wired bus rails, started light wiring harness.

2014-01-07: Testing, Coding, Hardware, Programmer's Front Panel, Firmware

Debugging DFP with the help of the simavr framework. The run/stop/step/microstep state machine now works properly.

2014-01-07: Construction, Hardware, Debugging Front Panel

Third construction session for Board 1. Wired bus rails, started light wiring harness.

2014-01-06: Testing, Coding, Hardware, Programmer's Front Panel, Firmware

Debugging DFP with the help of the simavr framework.

2014-01-05: Testing, Coding, Hardware, Programmer's Front Panel, Firmware

Debugging DFP with the help of the simavr framework.

December 2013

2013-12-28: Testing, Coding, Hardware, Programmer's Front Panel, Firmware

Building DFP testbench with simavr.

2013-12-28: Construction, Hardware, Debugging Front Panel

Second construction session for Board 1. Placed sockets and bypass capacitors.

2013-12-27: Testing, Coding, Hardware, Programmer's Front Panel, Firmware

Building DFP testbench with simavr.

2013-12-25: Testing, Coding, Hardware, Programmer's Front Panel, Firmware

Building DFP testbench with simavr.

2013-12-24: Testing, Coding, Hardware, Programmer's Front Panel, Firmware

Building DFP testbench with simavr.

2013-12-23: Testing, Coding, Hardware, Programmer's Front Panel, Firmware

Building DFP testbench with simavr.

2013-12-22: Testing, Coding, Hardware, Programmer's Front Panel, Firmware

Building DFP testbench with simavr.

2013-12-22: Testing, Coding, Hardware, Programmer's Front Panel, Firmware

Building DFP testbench with simavr.

2013-12-21: Testing, Coding, Hardware, Programmer's Front Panel, Firmware

Investigating DFP testbench with simavr.

2013-12-20: Coding, Hardware, Programmer's Front Panel, Firmware

DFP (former PFP) Firmware writing.

2013-12-17: Coding, Hardware, Programmer's Front Panel, Firmware

DFP (former PFP) Firmware writing.

2013-12-17: Coding, Hardware, Programmer's Front Panel, Firmware

DFP (former PFP) Firmware writing.

2013-12-16: Coding, Hardware, Programmer's Front Panel, Firmware

DFP (former PFP) Firmware writing.

2013-12-15: Coding, Hardware, Programmer's Front Panel, Firmware

DFP (former PFP) Firmware writing.

2013-12-14: Coding, Hardware, Programmer's Front Panel, Firmware

DFP (former PFP) Firmware writing.

2013-12-13: Coding, Hardware, Programmer's Front Panel, Firmware

DFP (former PFP) Firmware writing. Switched MCU to Atmega328P (from Atmega168) because the firmware will definitely need more than 16k. C is quite bloated in comparison to Assembly. There really isn't that much functionality in there.

2013-12-12: Coding, Hardware, Programmer's Front Panel, Firmware

DFP (former PFP) Firmware writing.

2013-12-07: Construction, Hardware, Debugging Front Panel

Third wiring session for board 2.

2013-12-06: Construction, Hardware, Debugging Front Panel

Second wiring session for board 2.

2013-12-05: Construction, Hardware, Debugging Front Panel

Initial work on board 2 of the front panel. Placed sockets, wires power rails. Started wiring.

November 2013

2013-11-29: Coding, Hardware, Programmer's Front Panel, Firmware

Yet more work on the PFP firmware. Documented some of the reset/start/stop/step clock-synchronous state machine, coded some firmware functions to control it.

2013-11-29: Coding, Hardware, Programmer's Front Panel, Firmware

Yet more work on the PFP firmware. Documented some of the reset/start/stop/step clock-synchronous state machine, coded some firmware functions to control it.

2013-11-23: Coding, Hardware, Programmer's Front Panel, Firmware

Worked on the PFP firmware. Compressed strings for a better fit in the 16k MCU.

2013-11-23: Coding, Hardware, Programmer's Front Panel, Firmware

More work on the PFP firmware.

2013-11-17: Construction, Hardware, Debugging Front Panel

Completed final layout of both DFP boards.

2013-11-17: Miscellaneous

Fixed dates in Changelog.

2013-11-16: Construction, Hardware, Programmer's Front Panel

Wired the switches to the switch break-out board.

2013-11-15: Design, Hardware, Programmer's Front Panel

Reworked the front panel assembly, preparing for laser cutting on acrylic. The LED modules fit on the LED module assembly, and the switches are fastened to a smaller switch sub-assembly, on spacers. The front panel fascia then attaches to the LED assembly completing the design.

2013-11-15: Construction, Hardware, Programmer's Front Panel

Rewired the switch side of the switch assembly with kynar wire.

2013-11-09: Design, Hardware, Programmer's Front Panel

Redesigned the front panel fascia with the key locks moved to the bottom and the µCB display to the left of the IR (so it appears as the IR MSB nybble, which it is).

2013-11-09: Miscellaneous

Created CFT Project logo, version 2. This is cleaner, and probably renders better on the CFT itself.

2013-11-08: Design, Hardware, Programmer's Front Panel

Second attempt to separate the PFP into two boards. This one uses a 13 IC daughterboard.

2013-11-08: Setbacks, Construction, Hardware, Programmer's Front Panel

Wired half of the front panel switch assembly before realising the loom was laid out the wrong way. I will have to do this all over. Separated flat cable turned out to be aesthetically displeasing, anyway. The next wiring attempt will use Kynar wire. Easier to bundle into a loom and easier to deal with. The wires may terminate on a small PCB with a 50-pin female socket, which will in turn connect to the PFP board using flat cable.

2013-11-03: Coding, Hardware, Programmer's Front Panel, Firmware

Worked on the PFP/DEB joint firmware.

2013-11-03: Setbacks, Design, Hardware, Processor Board 1

Discovered a potential race condition in the interrupt state machine: if interrupts are re-enabled right before an RTI macro, there is a very minor chance the ISR will be re-entered before it exits. Like the PDP-8, the CFT is non-reentrant, and this can cause issues. The flaw can be fixed in microcode (by finding some place to add an atomic RTI instruction), or in software, by saving the ISR return address onto a stack (the Forth Return stack is an ideal choice). The latter choice is easier, of course, although it increases interrupt latency.

2013-11-02: Coding, Hardware, Programmer's Front Panel, Firmware

Worked on the PFP/DEB joint firmware.

2013-11-01: Construction, Hardware

Cleaned all four processor boards.

October 2013

2013-10-31: Orders

Mouser order with PFP/DEB components arrived. The order also included Intersil 82C54 ICs needed to build the timer board and a second 16C2550 dual UART for the second half of the TTY board. I am now stocked to build the processor, PFP/DEB, interrupt controller, timer and IDE host adaptor boards.

2013-10-31: Construction, Hardware, Programmer's Front Panel

Crimped the Molex side of the front panel lights wiring loom (190 hand-crimped pins).

2013-10-30: Coding, Hardware, Programmer's Front Panel, Firmware

Worked on the PFP/DEB joint firmware.

2013-10-30: Orders

The ribbon cable I ordered on Ebay was probably lost en route. Jumped the gun and bought 10m of 50-way ribbon from the high street. The price was comparable.

2013-10-28: Construction, Hardware, Processor Board 3

Programmed and labeled Flash ROMs.

2013-10-28: Orders

Ordered additional components needed for the PFP/DEB board.

2013-10-24: Coding, Software, Filesystem

Added file removal support. 2013p-10-27 AC .

2013-10-24: Construction, Hardware, Processor Board 3

Finished construction of PB3.

2013-10-24: Coding, Software, ROM, Forth

Fixed TTY input bug that would only read one character per interrupt from TTY FIFOs.

2013-10-22: Coding, Software, Filesystem

Added file extraction support and debugged file writing. cftdt now has the essential features needed to create CFT disk images, with the exception of file deletion (which won't be needed until the CFT side can create and write files).

2013-10-21: Coding, Software, Filesystem

Restored C filesystem code functionality: cftdt can now create Level 0, 1 and 2 files and can dump filesystem blocks in hex.

2013-10-18: Construction, Hardware, Processor Board 2

Finished construction of PB2.

2013-10-17: Design, Hardware, Programmer's Front Panel

Completed schematics for amalgamated PFP & DEB board. 31 shift registers working as I/O expanders for the MCU! I can use the 6U (double-height) board and connectors previously meant to host the hand-routed PB2.

2013-10-17: Construction, Hardware, Processor Board 2

Placed and reflowed the bottom side of PB2.

2013-10-17: Construction, Hardware, Processor Board 3

Placed and reflowed the bottom side of PB3. The top side will have to be done when the hard to find 74HC670 arrive.

2013-10-15: Setbacks, Design, Hardware, Programmer's Front Panel

Rev C PFP schematics are done, but the chip count is too high to implement on even a double-sized PCB. Now considering merging the DEB (debugging) board and PFP so that I can use a microcontroller to implement switch debouncing, lock-out and registration (12 ICs) as well as the switch operation state machine (11 ICs) and part of the start/stop state machine (7 ICs).

This would remove some redundancies (e.g. both PFP and DEB implement HALT instructions), and possibly allow a ‘virtual’ front panel where the computer may be debugged and operated via a serial port.

The lights would still be driven directly by hardware, of course, since the MCU would be too slow to update them all (and not have anywhere near the enough I/O pins).

2013-10-10: Orders

Ordered components for PB2, PB3 and PFP boards, plus leftover parts for wiring the front panel itself.

2013-10-09: Design, Hardware, Programmer's Front Panel

Worked on Front Panel schematics. Started splitting PFP into PFP controller, switch break-out board and light break-out board. All three are through-hole.

2013-10-09: Orders

Generated BOM for PB2, PB3 and PFP. Ordered parts for PB2, PB3 and PFP.

2013-10-08: Orders

PB3 arrived.

2013-10-07: Design, Hardware, Programmer's Front Panel

Worked on Front Panel schematics.

2013-10-05: Design, Hardware, Programmer's Front Panel

Worked on Front Panel schematics.

September 2013

2013-09-25: Setbacks, Testing, Hardware, Processor Board 0

OPIF0 and FL are buffered but not connected to the front panel connector on PB0. There is a single spare pin (pin 38, previously grounded), now assigned to OPIF0 in the revision F PB0 board. This is less a problem than it seems, because both OPIF0 and FL are present on the control bus, and can be buffered and forwarded over to the control panel lights on the control panel controller (PFP) board.

2013-09-25: Design, Hardware, Programmer's Front Panel

Worked on Front Panel schematics.

2013-09-25: Orders

PB2 arrived.

2013-09-24: Design, Hardware, Programmer's Front Panel

Drafted rack mount case outlines, started changing front panel to fit.

2013-09-21: Design, Hardware, Programmer's Front Panel

Fixed issues with front panel assembly diagram.

2013-09-21: Orders

PB3 ordered.

2013-09-20: Construction, Hardware, Programmer's Front Panel

Constructed temporary front panel out of cardboard. Switches and lights are still unwired.

2013-09-17: Orders

Screw and front panel hardware has arrived.

2013-09-15: Design, Hardware, Video Display Board

Reworked VDU board from scratch, added ESD protection.

2013-09-14: Design, Hardware, Processor Board 3

Touched up PB3. Board is now ready for ordering. Rendered board.

2013-09-14: Design, Hardware, Prototyping Board

Completed prototyping board. Rendered top side of board.

2013-09-06: Construction, Hardware, Processor Board 1

Populated through-hole components. Patched pull-up issue for SBL muxes. PB1 is now complete.

2013-09-06: Orders

Ordered PB2 PCBs.

2013-09-05: Setbacks, Testing, Hardware, Processor Board 1

Outputs of SBL muxes are not pulled up (they are tristated when idle). This implies the three-input NOR gate is superfluous too, but better safe than sorry (the external input, ENDEXT#, could be pulled up by mistake).

2013-09-05: Construction, Hardware, Processor Board 1

Finished top side of PB1, surface mount components only.

2013-09-05: Testing, Hardware, Processor Board 1

Drew up PB1 testing plan.

2013-09-05: Orders

Screws and front panel hardware.

2013-09-04: Documentation, Extra

Wrote brief description of img2vdu output format.

2013-09-04: Coding, Software, Filesystem

C Filesystem code will now compile. Clean ups. Beginnings of rewriting of the lost code.

2013-09-01: Testing, Hardware, Processor Board 0

Uploaded video of PB0 testing to YouTube.

August 2013

2013-08-30: Milestone, Testing, Hardware, Processor Board 0

PB0 passes passive tests and most active tests.

2013-08-29: Testing, Hardware, Processor Board 0

Drew up PB0 testing plan.

2013-08-29: Construction, Hardware, Processor Board 0

Burned Microcode EEPROMs.

2013-08-28: Construction, Hardware, Processor Board 0

Placed and soldered top side of Processor Board 1.

2013-08-27: Construction, Hardware, Programmer's Front Panel, Light Assembly, LED Boards

Completed last remaining front panel boards. Tested all eight boards.

2013-08-27: Construction, Hardware, Processor Board 0

Placed and soldered bottom side of Processor Board 0.

2013-08-26: Tools

Improvements to the image-to-VDU converter. First revision of the VDU image format. The converter now outputs files in this format too, either binaries or as CFT Assembler source.

2013-08-25: Tools

First revision of the image-to-VDU converter. It can handle multicolour and graphics modes for now, and procuces either image format simulating what the VDU displays, or VDU-format files in CFT Assembly or binary formats.

2013-08-23: Orders

Mouser order with PB0 and PB1 components has arrived.

2013-08-22: Tools

Recreated subversion repository with new versions of all files.

2013-08-22: Orders

Cleared PB0 and PB1 boards through customs, at the cost of two hours, eleven seperate steps in three buildings, and 75% the value of the boards in various taxes.

2013-08-20: Tools

Recreated subversion repository with new versions of all files.

2013-08-19: Miscellaneous

Data recovered. Didn't bother with the 8×8 font which represents a small amount of effort (early revisions of just the ASCII characters done).

2013-08-19: Documentation

Added BOM for front panel to documentation.

2013-08-19: Orders

Ordered SMT components for the printed versions of the CFT PB0 and PB1.

2013-08-17: Setbacks

Rsync accident. Accidentally deleted all files created in the past two weeks, including some filesystem code, the completed reference card, the 8×8 font and the SpeakJet® experiment code.

2013-08-16: Setbacks, Orders

CFT PB0 and PB1 boards arrived in Athens and are stuck in Greek customs hell.

2013-08-16: Testing, Hardware, SpeakJet

Breadboarded and tested the SpeakJet® chip.

2013-08-11: Documentation, CFT Book

Minor fixes to the Data Storage (filesystem description) chapter.

2013-08-11: Coding, Software, Filesystem

C Filesystem code can now create, read and write Level 0 and Level 1 files.

2013-08-10: Setbacks, Design, Hardware, Processor Board 1

W# does not tri-state when the processor is halted. Will have to fix using a tri-state buffer.

2013-08-10: Coding, Software, Filesystem

C Filesystem code can now create, read and write Level 0 files.

2013-08-09: Documentation, Reference Card

Minor error corrections.

2013-08-09: Documentation, CFT Book

Minor fixes to the Assembler and programming model chapter.

2013-08-09: Coding, Software, ROM

First revision of an ASCII 8×8 font.

2013-08-07: Documentation, Reference Card

Produced a bus and instruction set reference card in text, postscript and PDF.

2013-08-06: Orders

Ordered new PB0 and PB1 boards from Smart Prototyping.

July 2013

2013-07-28: Orders

SpeakJet® chips delivered.

2013-07-23: Design, Hardware, Processor Board 2

Minor changes to the board layout. Signal conditioning. Re-rendered board.

2013-07-23: Design, Hardware, Processor Board 3

Minor changes to the board layout. Fixed minor issues with component/label placement. Signal conditioning. Re-rendered board.

2013-07-23: Orders

SpeakJet® chips ordered.

2013-07-22: Documentation, CFT Book

Documented new Control Bus signals.

2013-07-22: Design, Hardware, Processor Board 0

Minor changes to the board layout.

2013-07-22: Design, Hardware, Processor Board 1

Minor changes to the board layout. Signal conditioning. Re-rendered board.

2013-07-20: Testing, Design, Hardware

Fixed Verilog testbenches for new structures. Tests on the new control bus now pass.

2013-07-20: Design, Hardware, Processor Board 0

Added pull-ups/pull-downs so the board can be tested on its own. The new testing scheme involves building and testing boards PB0-3 incrementally.

2013-07-20: Design, Hardware, Processor Board 1

Minor changes to the board layout.

2013-07-20: Design, Hardware, Processor Board 2

Minor changes to the board layout.

2013-07-20: Design, Hardware, Processor Board 3

Minor changes to the board layout.

2013-07-20: Testing, Construction, Hardware, Processor Board 1

Built and tested the clock generator and write strobe generation logic to verify they work as expected on real hardware.

2013-07-19: Orders, Tools

More solder paste (in syringes), a manual applicator with plunger and an IR thermometer have been delivered. They should make hot-air soldering easier.

2013-07-19: Design, Hardware, Processor Board 1

Finished routing PB0. Rendered result.

2013-07-19: Design, Hardware, Processor Board 2

Minor re-routing for amended control and expansion bus signals.

2013-07-19: Design, Hardware, Processor Board 3

Minor re-routing for amended control and expansion bus signals.

2013-07-18: Design, Hardware, Processor Board 1

Routing PB0.

2013-07-17: Design, Hardware, Processor Board 0

Minor routing fixes. Re-rendered.

2013-07-17: Design, Hardware, Processor Board 1

Placing PB1 almost from scratch. Without the unic decoders and separate microcode store connector, there's a lot more space for routing and the process is expect to be considerably less painful than previous revisions of the board.

2013-07-16: Design, Hardware, Processor Board 0

Finished routing revision E PB0. Board passes DRC and ERC. Rendered proofs of the board.

2013-07-15: Design, Hardware, Processor Board 0

Routing revision E with the new layout and no microcode connector.

2013-07-14: Design, Hardware, Processor Board 0

Realised need for pull-ups for all input signals. Added pull-ups. Since I'm reworking PB0 anyway, investigating removing the microcode store connector altogether, in favour of the control bus. Most of the signals are there anyway. However, this requires moving the unit decoders to PB0 too. Added SMT resistor arrays for impedance matching on all outputs.

2013-07-14: Design, Hardware, Processor Board 1

Reworking PB1 to remove microcode store connector in favour of the control bus. Through-hole resistor nets to be removed in favour of SMT resistor arrays.

2013-07-14: Setbacks, Design, Hardware, Processor Board 2

PB2 was not receiving DEC# signal from the microcode store because DEC# was never assigned a control bus pin! Reworked control bus to add this. Merged INCCPL# and DECCPL# signals into ACCPL# using an AND gate on PB2.

2013-07-14: Design, Hardware, Processor Board 3

PB3 must be reworked to incorporate the merged INCCPL# and DECCPL# signals. This may save up to two gates.

2013-07-14: Design, Hardware, Control Bus

Reworking signals needed for the control bus, merging in signals used in the microcode connector with a view to removing it altogether.

2013-07-14: Simulation, Design, Hardware

Refactored Verilog code to account for changes in processor design.

2013-07-13: Design, Hardware, Processor Board 1

Investigating use of the DS1805 I²C-programmable clock generator on PB1. It'll allow the processor frequency to be changed for testing, and also takes up less space than a traditional oscillator.

2013-07-13: Design, Hardware, Video Display Board

Investigating use of the DS1805L I²C-programmable clock generator on the VDU. The CPLD can program it via I²C and we can support arbitrary pixel clocks up to 33 MHz (pixel clocks are currently half the frequency of the CPLD clock). Mostly, it'll be able to generate lower frequencies to drive, for instance, old-style 15 kHz RGB monitors (at lower resolutions, of course).

2013-07-12: Setbacks, Design, Hardware, Processor Board 0, Routing

The wrong version of PB0 was printed! The CAM job processed the right files (revision C), but the ZIP script zipped up revision A, even after I verified the Gerbers. I'll need to re-order PB0. On the upside, I fixed the IRQS# bug in the µCB extension and rerouted the board using the TSSOP-48 16-bit buffers I ordered by mistake. The new PB0 passes ERC and DRC and has been rendered front and back, as usual.

2013-07-11: Design, Hardware, Processor Board 1, Routing

PB1 routing.

2013-07-11: Orders, Milestone

Processor Board 0 (the Microcode Store) PCBs arrive.

2013-07-10: Design, Hardware, Processor Board 1, Routing

PB1 routing.

2013-07-09: Changelog, Documentation, Progress

Updated Changelog with entries from Subversion log.

2013-07-09: Design, Hardware, Processor Board 1, Routing

PB1 routing. Considering re-routing from scratch.

2013-07-08: Changelog, Documentation, Progress

Generated Changelog file using entries from Facebook page.

2013-07-07: Setbacks, Design, Hardware, Processor Board 0

Bug discovered in PB0 µCB extension: executing the Interrupt Service Routing cancels any temporarily set bank. Proposed fix is to AND the INT input to the microcode store with the temporary bank enable, making a temporary bank switch and the instruction following it an atomic operation (as far as interrupts are concerned). The design for this is still not in place and will have to be patched in because the PB0 boards have already been shipped.

2013-07-07: Design, Hardware, Processor Board 1, Routing

PB1 routing.

2013-07-07: Design, Processor Board 2, Schematics

Changed semantics of MBU's enable bit. 0 is on, 1 is off. Makes it faster to change banks (no additional OR is required). Makes it harder to turn off banking, which is a very uncommon operation.

2013-07-07: Coding, Emulator

Synchronised emulator with new I/O map.

2013-07-07: Coding, Emulator

Rewrote MBU emulation.

2013-07-07: Coding, Software, ROM, Forth

Changed code to accommodate new I/O map.

2013-07-06: Construction, Hardware, Programmer's Front Panel, Light Assembly, LED Boards

6 of 8 boards populated with SMD parts.

2013-07-01: Design, Hardware, Programmer's Front Panel

Drew panel assembly cross-section.

2013-07-01: Design, Hardware, Processor Board 1, Routing

PB1 routing.

June 2013

2013-06-20: Construction, Hardware, Programmer's Front Panel, Light Assembly, Switch Assembly

Spray-painted switch paddles for front panel switches.

2013-06-20: Design, Hardware, Processor Board 1, Routing

PB1 routing.

2013-06-17: Orders

Mouser order with components for the panel and latest PB0 arrived.

2013-06-17: Setbacks, Orders

I ordered the wrong package for the rather expensive 16-bit buffers used for the front panel. They're TSSOP48 which is smaller than SSOP48 (which is small enough). A few single-gate ICs were ordered in three-input versions rather than two-input versions. Will work into incorporating the mis-ordered parts into other boards.

2013-06-14: Meta, Documentation, CFT Book

Renamed processor boards. The boards are now PB0 (formerly the Microcode Board), PB1 (Processor Board A), PB2 (Processor Board B) and PB3 (Processor Board C).

2013-06-14: Design, Hardware, Processor Board 0

Moved entire sequencer to PB0. Rerouted.

2013-06-14: Preparation, Hardware, Processor Board 0

Produced CAM jobs for printing PB0. Proofed land patterns for SOIC ICs, 0805 passives and other components.

2013-06-14: Orders

Ordered PB0 boards from Smart Prototyping.

2013-06-14: Design, Hardware, Programmer's Front Panel, Light Assembly

Designing layout of light assembly using LED modules.

2013-06-07: Orders, Milestone

First PCBs (the front panel modules) arrive from Smart Prototyping and they look good. Got a yield of thirteen boards, while ten were ordered.

2013-06-07: Design, Hardware, Programmer's Front Panel, Light Assembly

Designing layout of light assembly using LED modules.

2013-06-01: Tools

Writing a PC-side tool to manage and access CFT disk images, disk labels and filesystems. Developing the algorithms will provide a basis for coding them in CFT Assembly for inclusion in the ROM.

May 2013

2013-05-31: Design, Hardware, Processor Board 3

‘Processor Board C’ routed.

2013-05-23: Orders

A batch of front panel modules is on its way from China. The boards serve as a test of the fab facility's quality.

2013-05-22: Design, Hardware, Processor Board 2

Touched up design of ‘Processor Board B’, the register board. Rendered the board.

2013-05-22: Design, Hardware, Processor Board 0

Preparing Microcode Board for printing. Routed another version, rendered result.

2013-05-17: Setbacks, Construction, Hardware, Processor Board 2

Spent five hours wiring up the register board. Decided 900 nets will take too long to wire and will make issues almost impossible to find and fix. Resigned to making PCBs of all four processor boards.

2013-05-14: Testing, Simulation, Design, Hardware

Verilog verification of processor passes test suite.

2013-05-08: Design, Hardware, Programmer's Front Panel, Light Assembly, LED Boards

Revived the idea of the panel LED assembly on PCB modules. Eight single-sided modules of 4×5 LEDs were designed. This is Revision C of the front panel module.

2013-05-06: Preparation, Hardware, Processor Board 0

Microcode card job files ready for fabrication.

April 2013

2013-04-22: Tools

Ordered Digital Storage Oscilloscope.

2013-04-02: Design, Hardware, Processor Board 2

Routing PB2 (as ‘Processor board B’, the register board) on a 16×10cm EuroBoard.

March 2013

2013-03-30: Testing, Simulation, Design, Hardware

Rewrote tests for the hardware, including new ones to cover design changes. Hardware now covered 100% with exhaustive tests. Testing revealed numerous annoying hardware bugs that were fixed easily.

2013-03-21: Coding, Software, ROM

Coded 32-bit division. Whoever wrote a 24-bit division routine for a PDP-8 is an unsung hero. If my assembler didn't have macros I'd have gone crazy.

2013-03-12: Setbacks, Testing, Design, Hardware

Glitch found while testing processor as a whole.

February 2013

2013-02-26: Design, Hardware, Processor Board 0

Microcode personality board renamed to Microcode Board, hosts microcode store and µBC extension. Cleaned up schematics and routed Rev A. Rendered routed board.

2013-02-20: Setbacks, Testing, Hardware, Processor Board 1

Auto-Index Logic bug found. Any Indirect mode instruction immediately following an Autoindex instruction changes into an Autoindex instruction too, no matter what location is being accessed.

2013-02-17: Documentation, Reference Card

Toyed with the idea of a Bowen-style reference card.

2013-02-17: Documentation, Website

GeSHI PHP syntax highlighter mode for CFT Assembly.

2013-02-16: Documentation, Website

Wrote CFT microcode-level simulator in Javascript. Shows Front Panel and simple output device, runs considerably slower than real hardware.

2013-02-09: Coding, Software, Microcode

Updated to Microcode version 6.

2013-02-06: Design, Software, Microcode

Microcode version 6 being designed with additional instructions: JMPII (doubly-indirect JUMP, i.e. the Forth ENTER instruction) and POP to help with Forth.

2013-02-06: Miscellaneous

Georgios Fountis donated a book on advanced Forth techniques.

2013-02-04: Coding, Emulator

Worked on emulator, fixing issues and refactoring code. Version 0.7 now available.

January 2013

2013-01-31: Construction, Hardware, Processor Board 1

Started layout of PB2 as ‘Processor Board B’ on double-width Euroboard.

2013-01-24: Simulation, Design, Hardware, Video Display Board

VDU fully synehtesisable and tested using JTAG interface. Video of JTAG-based demo uploaded to YouTube.

2013-01-01: Simulation, Design, Hardware, Video Display Board

Added VDU support for SDRAM. Not needed for final project, but necessary to test the VDU on the dev board (which has no SRAM memory).

2013-01-01: Design, Hardware, Video Display Board

Design changed to use 640×480 resolution rather than initial 640×400 because of better support from available monitors. VDU now offers 40×30 and 80×30 text, and high resolution graphics up to 640×480.

December 2012

2012-12-29: Simulation, Design, Hardware, Video Display Board

VDU design now partly synthesisable. Testing on a physical Terasic® DE-0 Nano board with an Altera® FPGA. First test patterns generated at 640×400 with 64 colours.

2012-12-16: Simulation, Design, Hardware, Video Display Board

The VDU board passes ERC and DRC tests.

2012-12-16: Design, Hardware, Video Display Board

Rendered Altera® CPLD VDU board revision E with PS/2 and Sun keyboard/mouse ports.

2012-12-15: Documentation, CFT Book

The CFT Book is now 381 pages long and includes documentation on the VDU.

2012-12-06: Simulation, Coding, Emulator

Implemented VDU in emulator for feasibility testing. It works well.

2012-12-06: Design, Hardware, Video Display Board

Altera® CPLD version of the VDU simulating cleanly.

November 2012

2012-11-28: Design, Hardware, Video Display Board

Debugged and simulated VDU design.

2012-11-28: Design, Hardware, Video Display Board

Xilinx® software is getting in the way and crashing on Linux.

2012-11-28: Setbacks, Design, Hardware, Video Display Board

VDU design will not fit the chosen Xilinx® CPLD part, so 5V tolerance is no longer an option. Switched camps using an Altera® CP9500XL CPLD.

2012-11-21: Design, Hardware, Video Display Board

Horizontal phase control circuit allows for smooth horizontal scrolling.

2012-11-19: Design, Hardware, Video Display Board

Verified VDU design fits a Xilinx® XC95288XL CPLD.

2012-11-18: Simulation, Design, Hardware, Video Display Board

Simulated VDU CPLD generating correct 40-column test pattern.

2012-11-18: Simulation, Design, Hardware, Video Display Board

Split-screen working.

2012-11-17: Setbacks, Design, Hardware, Video Display Board

Timing tolerances are too tight for 74HC family. VDU card switched to Xilinx® CPLD, discrete logic abandoned.

2012-11-17: Design, Hardware, Video Display Board

CPLD-based VDU card schematics and routing.

2012-11-17: Design, Hardware, Video Display Board

First rendering of VDU card.

2012-11-10: Design, Hardware, Video Display Board

Debugging timing issues.

October 2012

2012-10-31: Design, Hardware, I/O Board

Simulated test of cassette tape encoding. The encoding is similar to Sinclair's and sounds much like a faster version of the ZX-Spectrum's tape encoding.

2012-10-28: Milestone, Simulation, Design, Hardware, Video Display Board

First VDU image displaying in simulations.

2012-10-27: Simulation, Design, Hardware, Video Display Board

Verilog simulations of parts of the VDU.

2012-10-26: Tools, Simulation, Design, Hardware, Video Display Board

Created monitor emulator to verify VDU designs on.

2012-10-26: Design, Hardware, Video Display Board

Verilog simulations of parts of the VDU.

2012-10-24: Design, Hardware, Video Display Board

Initial Verilog simulations of parts of the VDU.

2012-10-08: Design, Hardware, I/O Board

Designed cassette tape interface to add to the IO Board.

2012-10-05: Documentation, CFT Book

Worked on documentation.

2012-10-04: Documentation, Software, Filesystem

Documented filesystem structures.

2012-10-04: Design, Hardware, Floppy Drive Controller

First draft of a floppy controller board.

September 2012

2012-09-27: Design, Hardware, Video Display Board

Drafting schematics of the VDU board.

2012-09-20: Documentation, CFT Book

First appearance of the CFT Book as a single entity, rather than the various separate guides. The initial version is 309 pages long.

2012-09-18: Setbacks, Tools

Potential transmission-line and termination issues with backplane mandate a digital storage oscilloscope for debugging. Construction temporarily on hold while I budget.

2012-09-10: Documentation, Progress

Created first edition of CFT Progress Poster/Infographic.

2012-09-06: Design, Hardware, Control Bus

Programmatically extracted signals needed for the control bus using Python script and the processor's netlist.

2012-09-05: Setbacks, Testing, Hardware, Memory Board

Backplane termination resistors burn parts of DEB and MEM boards. Replaced dead memory on MEM board, but one I²C GPIO chip now missing from DEB board.

August 2012

2012-08-31: Construction, Hardware, Memory Board

Completed construction of the MEM board. 512kW of flash ROM and RAM, debugging LEDs and pull-down resistors for when MBU is missing.

2012-08-29: Setbacks, Construction, Hardware, Debugging Board

MOS termination resistors on backplane too strong for CMOS drivers, getting strange readings from DEB board. Resistors getting unacceptably hot in operation.

2012-08-26: Coding, Hardware, Debugging Board, Firmware

Completed first revision of the DEB firmware.

2012-08-24: Construction, Hardware, Debugging Board

Completed construction of DEB card.

2012-08-22: Tools

Updated Flashprog software. Added PLCC32 socket for CFT Flash ROMs.

2012-08-21: Orders

AY-3-8910 chips arrive.

2012-08-17: Documentation, Hardware, Debugging Board

Updated specification for the DEB board.

2012-08-16: Coding, Emulator

Added VDU support to the emulator. Coded various other improvements.

2012-08-15: Orders, Milestone

First round of components ordered.

2012-08-09: Documentation, Hardware

Designed layout templates for double-width DIP boards.

2012-08-09: Design, Hardware, Processor Board 1

Laid out PB1 as ‘Processor Board A’ with DIP components.

2012-08-09: Design, Hardware, Processor Board 2

Laid out PB2 as ‘Processor Board B’ with DIP components.

2012-08-09: Design, Hardware, Processor Board 3

Laid out PB3 as ‘Processor Board C’ with DIP components.

2012-08-06: Design, Hardware, Debugging Board

Finished design of debugging board.

2012-08-06: Documentation, Hardware, Debugging Board

Rendered DEB board.

2012-08-06: Documentation, Hardware, Debugging Board

Rendered DEB board.

2012-08-04: Documentation, Website

Started @CFTProject twitter account.

July 2012

2012-07-29: Documentation, Hardware, Sound Board

Drafted specification for compact music file format to help ripping music from Z80 executables to compact files for the CFT.

2012-07-28: Design, Hardware, Sound Board

First draft of sound card incorporating an GI AY-3-8910 chip.

2012-07-23: Design, Hardware, Processor Board 0

Simplified clock generator.

2012-07-20: Documentation, Website

Added Flickr set, opened it to the public.

2012-07-13: Design, Hardware, Programmer's Front Panel

Designed front panel layout version 4 (4U, three bank).

2012-07-12: Documentation, Hardware, Programmer's Front Panel

Updated front panel specification.

2012-07-01: Design, Hardware, Video Display Board

Initial design of a VDU board.

May 2012

2012-05-14: Coding, Software, ROM, Forth

Completed DOES> implementation.

2012-05-12: Coding, Software, ROM, Forth

Many changes to the word set.

2012-05-12: Documentation, Gallery

Added more screenshots.

2012-05-12: Documentation, CFT Book

Released Revision F of the Programming Guide.

April 2012

2012-04-19: Coding, Software, ROM, Forth

Additional changes to implement more words and more IDE support.

2012-04-19: Coding, Emulator

IDE emulation improvements. Minor changes to support updated hardware. Added more debugging info.

2012-04-19: Coding, Cross-Assembler

Minor bug fixes and .reg directive support.

2012-04-16: Coding, Software, ROM

Major changes to the ROM to facilitate device detection/initialisation etc.

2012-04-16: Coding, Emulator

Major changes to add device drivers, clean up code and implement banked memory.

2012-04-14: Setbacks, Coding, Software, Microcode

Autoindex bug located in the IN instruction. Fixed.

2012-04-14: Coding, Emulator

Work on attaching new I/O devices.

2012-04-14: Coding, Software, ROM, Forth

Numerous additions to dictionary. IDE test code. Minor changes to the user area.

2012-04-12: Coding, Software, ROM, Forth

Considerable amounts of work done. Compiler is now in place.

2012-04-11: Coding, Software, ROM, Forth

Forth 83 multiple vocabulary support is now in place.

2012-04-06: Coding, Software, ROM, Forth

More vocabulary work. Renumbering to fit ONLY vocabulary.

2012-04-05: Coding, Software, ROM, Forth

Major additions for debugging, testing. Added compiler words, some defining words and more vocabulary functionality.

2012-04-02: Coding, Software, ROM, Forth

Most of the interpreter is now in place, including error handling.

2012-04-02: Coding, Emulator

Fixed issues with excessive CPU power due to tight select(2) loops. Added more I/O. Fixed fetch/execute cycle detection.

March 2012

2012-03-30: Coding, Software, ROM, Forth

Major changes to the dictionary structure. Coded user area, added some vocabulary support. Lots of refactoring.

2012-03-26: Coding, Software, ROM, Forth

Various bits of Forth work.

2012-03-22: Coding, Software, ROM, Forth

Implemented algorithms and unit tests for unsigned, symmetric and floored division in 16 and 32 bits. For now, Forth algorithm tests are shared with the Verilog tests (and executed with the Verilog simulator).

2012-03-22: Coding, Software, ROM, Forth

Bug fixes and implementation of various Forth words.

2012-03-18: Testing, Design, Hardware

Added more hardware tests.

2012-03-18: Design, Hardware

Imported mkskiptable, meant to speed up minor operation instructions. The functionality is currently too complex, so not used.

2012-03-18: Coding, Software, ROM

Bug fixes and Forth work.

2012-03-12: Documentation, Website

Created Facebook page.

2012-03-12: Coding, Software, ROM, Forth

More Forth primitives. Code reorganisation.

2012-03-12: Coding, Software, ROM

First OS traps added.

2012-03-09: Tools

Cleaning up Subversion repository. Removing temporary files.

2012-03-09: Coding, Software, ROM, Forth

Coded core ROM Forth words (and then some).

February 2012

2012-02-25: Design, Hardware

Completed CFT schematic collection into a very large Eagle file. This will help keep signal names constant, and will eventually aid DRC.

2012-02-17: Design, Hardware

Fixed ALU bugs. Recoded Verilog ROM-ALU to handle the new ALU design.

2012-02-17: Design, Hardware

Updated schematics, fixing numerous issues (including the ALU one).

2012-02-17: Testing, Design, Hardware

Added batch tests for the ALU.

2012-02-17: Documentation, Extra

Added Forth documentation (external to the project).

2012-02-17: Documentation, Extra

Added FlashForth distribution (also external).

2012-02-17: Coding, Software, Filesystem

Work on the filesystem code.

2012-02-14: Design, Hardware

Corrected issues with the ROM-based ALU.

2012-02-14: Testing, Design, Hardware

Coded ALU test benches in Verilog.

2012-02-04: Design, Hardware, Clock/Timer/NVRAM Board

Drafting timer layout.

January 2012

2012-01-20: Design, Hardware, Programmer's Front Panel, Controller

Considerable amount of work on the front panel controller.

2012-01-20: Design, Hardware

Worked on the clock generator.

2012-01-16: Design, Hardware, Programmer's Front Panel, Controller

SMD test of front panel controller. Superseded design, now using new version of front panel controller.

2012-01-16: Design, Hardware, Programmer's Front Panel

Various changes and corrections to the front panel. itself.

2012-01-16: Documentation, Gallery

Added PNG files to the gallery.

2012-01-09: Tools

Added functionality to extract bills of materials from Eagle schematics.

2012-01-09: Documentation, CFT Book

Added BOM for front panel to documentation.

2012-01-09: Documentation, Extra

Added external documents useful for the development of the project (datasheets, etc).

2012-01-09: Coding, Software, Filesystem

First filesystem experiments.

2012-01-09: Design, Hardware, Programmer's Front Panel

Front Panel version 2 (rev B).

2012-01-09: Documentation, Hardware, Programmer's Front Panel

Front Panel Bill of Materials generated.

December 2011

2011-12-30: Tools

Cleaned up crud entries from Subversion repository.

2011-12-28: Coding, Cross-Assembler

Added macro and file inclusion support.

2011-12-28: Tools

Slight changes to Eagle3D board rendering options.

2011-12-28: Design, Hardware, Programmer's Front Panel, Controller

Rendered front panel controller.

2011-12-26: Design, Hardware, Programmer's Front Panel, Controller

Completed first revision of Front Panel Controller board.

2011-12-22: Design, Hardware, Programmer's Front Panel

Additional work on the front panel.

2011-12-21: Design, Hardware, Programmer's Front Panel

More work on the front panel and its documentation.

2011-12-19: Design, Hardware, Programmer's Front Panel

Further design and verification work on the panel.

2011-12-13: Design, Hardware, Programmer's Front Panel

First release candidate of the front panel.

2011-12-03: Design, Hardware, Programmer's Front Panel

First draft of the front panel.

2011-12-01: Design, Hardware, Programmer's Front Panel

Worked on Front Panel schematics.

November 2011

2011-11-30: Tools

Removed VHDL support and relevant directories. The project has been using Verilog for verification for a while.

2011-11-30: Miscellaneous

Created CFT Project logo.

2011-11-08: Tools

Released FlashProg hardware and software design.

October 2011

2011-10-25: Tools

Released mcasm (the Microcode Assembler).

2011-10-24: Tools

Released ROMtools, a Python library to generate complex function tables on multiple ROMs. This is used to generate the ALU tables.

September 2011

2011-09-02: Design, Hardware

More changes to the hardware and PCBs.

August 2011

2011-08-31: Design, Hardware

Changes to PCBs for new hardware style.

2011-08-30: Design, Hardware

Switched to ROM-based ALU.

2011-08-08: Design, Hardware

Many changes to the hardware design.

March 2011

2011-03-14: Design, Hardware

Major changes to support autoincrement mode, fix issues with the L flag (excessive toggling), rework microcode, uaddr vector, control vector, register types, etc.

2011-03-14: Design, Software, Microcode

Autoincrement now supported in LOAD.

2011-03-14: Design, Hardware

Playing around with Eagle schematics as a very early feasibility study.

2011-03-03: Tools

Created Subversion repository. Initial import of pre-existing code and data.

2011-03-03: Design, Hardware

Removed Page Register from CPU design.

2011-03-03: Design, Hardware

Changed MAR to '193-based register.

February 2011

2011-02-11: Design, Hardware

Earliest version of the ‘simple 16-bit CPU’ description, a direct descendant of the Fungus CPU. Still references 18-bit registers (like Fungus).

January 2011

2011-01-25: Design, Hardware

Earliest draft version of the ‘memory mapped stack machine’ CPU description referencing a PDP-8-like design, but with an 8 bit word.