This is the project log of the CFT project, updated as the project is being worked on. The changes aren't always published immediately, though. It's a bit dry, but it's probably your best bet for progress information!

There are 580 entries on the project log.

August 2016


Mouser order for PB1 arrived. Orders


Ordered components for PB1 from Mouser and eBay (for the SN74ACT1071 which Mouser doesn't stock). Orders


Solder paste has arrived. Orders


Revision G of the PB1 PCBs have arrived. Orders

July 2016


Ordered solder paste. Orders


Reworking the testing framework. Added two new testing targets: emulator (via the DFP), and hardware (also via the DFP, of course). Need to refactor the Verilog testbeds. With mostly working hardware, this is not strictly needed, but it should do it for completeness. Testing


Created Instagram. Documentation Web

Minor refurbishment of the Twitter account. Documentation Web

Ordered Revision G of the PB1 PCBs. Orders

June 2016


Writing documentation for the DFP. Started documenting the hardware, including Sketchup renders, PCBs, assemblies etc. Book Documentation


Writing documentation for the DFP. Started documenting the hardware, including Sketchup renders, PCBs, assemblies etc. Book Documentation

Discovered and fixed a minor bug in the DFP firmware (HALT instruction not being honoured while multistepping or tracing). Colourised error messages. Bugs DFP Testing

Writing documentation for the DFP. Started documenting the hardware, including Sketchup renders, PCBs, assemblies etc. Book Documentation

Discovered and fixed a minor bug in the DFP firmware (HALT instruction not being honoured while multistepping or tracing). Colourised error messages. Bugs DFP Testing


Writing documentation for the DFP. Book Documentation

Fixed a number of minor bugs in the DFP firmware. Bugs DFP Testing


Writing documentation for the DFP. Book Documentation

Fixed a number of minor bugs in the DFP firmware. Reflashed the physical DFP and performed a few tests on it. Bugs DFP Testing


Writing documentation for the DFP. Book Documentation

Fixed a number of minor bugs in the DFP firmware. Bugs DFP Testing


Writing documentation for the DFP. Book Documentation


Writing documentation for the DFP. Book Documentation

May 2016


Writing documentation for the DFP. Book Documentation

Worked on the DFP testing tool. DFP Testing


Writing documentation for the DFP. Book Documentation


Writing documentation for the DFP. Book Documentation


Finished pseudo-TTY code, so the emulator can be used to develop tests for the real, live CFT. The emulated DFP is still not fully implemented, but it's close enough to test things. Fixed minor bugs. Code Emulator

Fixed a number of minor bugs in the DFP firmware just by testing communications with the testing tool. Bugs DFP Testing

February 2016


Completed first update of the theoretical description chapter. Needs to be re-organised heavily. Book Documentation


Worked on the web edition of the Theoretical Description chapter. Book Documentation


Worked on reference resolving code, improved markup framework. Worked on the web edition of the Theoretical Description chapter. Book Documentation


Worked on the web edition of the Theoretical Description chapter. Book Documentation


Worked on the Web version of the documentation. Redid the Assembler chapter and worked on formatting code and styling. Debugged plenty of issues with the TeX to HTML conversion. Fixed spelling mistakes. Brought some of the content up to date. Book Documentation

Worked on the web edition of the Theoretical Description chapter. Book Documentation


Worked on the Web version of the documentation. Redid the Programming Model chapter. Worked on the styling. Added a little information and corrected mistakes. Book Documentation


Fixed bugs from previous day. The run/stop logic works fine now. Working on more integration of DFP features. Code Emulator

January 2016


Fixed minor layout issues on G PB1 board. Cons Hardware PB1

Added front panel and bus interrupt support to the emulated DFP. Working on run/stop logic and bus command integration. It's more complex than it looks because of the necessity for synchronisation and thread-safety. I may have to simplify things, but can't really change the firmware code so the separate thread is here to stay. Code Emulator


Verifying Rev G PB1 schematic and preparing to have it manufactured. Cons Hardware PB1

Added Switch Register support to the emulator and improved the virtual front panel. Continuing to implement virtual DFP integration. Code Emulator

November 2015


Worked on virtual reset circuitry. Thread synchronisation can be problematic for this stuff, since the DFP runs on its own thread. Using a system of simple messages to the emulator thread. Code Emulator


Worked out the previous ‘deadlock’ issue: it was OS blocking because the Emulator was opening a debugging pseudo-TTY which wasn't being read from. Once the OS PTY buffer got full, writes blocked blocking the entire DFP thread (but not the rest of the emulator). Code Emulator

September 2015


Solved serialisation bugs, implemented much more functionality. The DFP can now read and write to memory and I/O. Code Emulator


DFP firmware now has access to most of the Emulated CFT. Some operations still can't be performed. A couple of serialisation bugs have appeared. Code Emulator


Working on adding the full DFP firmware into the emulator. Code Emulator


Working on adding the full DFP firmware into the emulator. Code Emulator


DFP Firmware now running on the emulator! Still mostly throws ‘NOT IMPLEMENTED’ messages and has no access to the emulated machine. Code Emulator


Working on adding the full DFP firmware into the emulator. Code Emulator

August 2015


Working on adding the full DFP firmware into the emulator. Code Emulator


Working on adding the full DFP firmware into the emulator. DFP firmware now compiling as library and linking against the emulator. Code Emulator


Working on adding the full DFP firmware into the emulator. Code Emulator


Working on adding the full DFP firmware into the emulator. Code Emulator

July 2015


Produced CAM files for PB1, ready to reprint PCB. Bugs Cons Hardware PB1

June 2015


Progress with the revision G PB1 board. Bugs Cons Hardware PB1

May 2015


Updated the rev G PB1 schematic with the newest write circuitry bug fix (the added NOT gate so the circuit floats when HALT# is asserted, not the other way round). Bugs Cons Hardware PB1


Updates the CFT microcode-level emmulator to use the newest DFP addresses, so it can use the newest Assembly include files. Documentation Web

Now tha the Javascrpit emulator is so much faster, I've added short welcome messages to most of the sample ROM's programs, including a boot-up message. The ROM now showcases the Assembler (and instruction set) pretty well: it has macros, scopes, subroutines, extended instructions, the works. I've refactored the ROM to get rid of old cruft, cleaned and reformatted up the source, and annotated everything with comments. The ROM is now published on the web anyway. Code ROM Software


Patched PB1 write strobe circuitry. One last bug remaining: the circuit should tri-state when HALT# is de-asserted. It's currently doing the reverse (a NOT gate is needed). Bugs Cons Hardware PB1

Patched the DFP so it doesn't use open drain drivers for MEM#, IO#, R# and W#. One minor hardware patch needed: snip the ABOE# signal to board 2. This will permanently disable NOPROC mode, and the current AB-OE# signal will then be renamed to BUSEN#. Obviously, this will require changes to the DFP firmware. On the up side, with NOPROC mode removed, the firmware will be smaller. Bugs DFP Testing

April 2015


Worked on the documentation. It dawns on me that I should probably port the documentation to HTML, XML or somesuch instead and use LaTeX for the diagrams. I can then re-import it into LaTeX to generate PDFs — when/if I decide to do so. These days, HTML can be have more semantics than TeX!. Book Documentation


Added some content to the CFT Book (processor description). Corrected a few errors. Re-added the Javascript emulator with new text, including the ROM source code. Published the documentation on the live website. Book Documentation


More work on the CFT Book conversion, as well as the CFT section on the BedroomLAN site. Book Documentation


More work on the CFT Book conversion, as well as the CFT section on the BedroomLAN site. Book Documentation


More work on the CFT Book conversion, as well as the CFT section on the BedroomLAN site. Book Documentation


First drafts of The CFT Book (at least the non-empty chapters) are now online. Hyperlinks are stripped out of the documents and there's still need for plenty of CSS styling, but at least the information is online again. Book Documentation

March 2015


Much progress with the documentation converter. For now, it's generating a single, huge HTML file with proper markup including SVG images (but currently not maths). Once cross-chapter links are converted and a stylesheet is written, it will be possible to publish an early version of the documentation. Book Documentation


Additional work on the documentation converter. Puzzling out TeX Math to SVG conversion. Book Documentation


Started work on converting the CFT Book (HTML version) to Jinja 2 HTML suitable for the BedroomLAN site. Book Documentation

November 2014


Rewired control bus to fix issues with the DFP. Bugs DFP Testing

October 2014


Completed the PS/2 keyboard handler. Keyboard events are now read and inserted into the event queue of the current process. Code ROM Software


After not having been touched for a couple of weeks, the CFT hardware is failing diagnostics for the AC (IBUS trouble, possibly a short) and PC (it never changes, possibly WPC connection broken or shorted). DFP Board 2 is almost certainly to blame for this. Bugs DFP Testing

September 2014


Added the KBD Interrupt handler. The OS can now read from a PS/2 keyboard. Code ROM Software


Worked on the VDU/KBD driver. The driver has extremely rudimentary tty support. It can output characters (so the initial text-mode banner is visible) but not yet scroll, etc. Code cleanups. Code ROM Software


Work on the VDU driver for the OS. Code ROM Software

Documented the new interrupt state machine, including state diagrams and waveforms. Book Documentation


Reworked the Rev F PB1 schematics and PCB to include the fifth state in the interrupt state machine. Design Hardware PB1

Work on the VDU driver for the OS. Code ROM Software


Interrupt driven, FIFO-based I/O is going well, but I have struck my worst-case scenario: an interrupt being signalled between the SEI and RTI instructions, which means two things: (a) the ISR will have to re-entrant (or have a return stack), and (b) interrupts are coming in faster than the ISR can handle, even with just a TTY. Code ROM Setback Software


Work on interrupt-driven TTY I/O. Code ROM Software


Work on FIFOs and interrupt-driven TTY I/O. Code ROM Software


Work on the ROM. Modulo some more refactoring, I'm ready to start adding the ROM Forth interpreter back to the mix. The ROM Forth dictionary will be pared down to the essentials, so the interpreter, compiler and essential features can fit in 8kW. Forth 83 support can be added later, which will allow another 8kW for the language. Then, another 8kW should add support for most of the hardware. Code ROM Software


Finished the memory inspection code in the emulator and used it to track down an issue with the TTY driver code. Code Emulator

Since the DFP is working well with the processor, and it's the only bus-mastering device, and since the PB1 has so many bugs, I've all but decided to give up on tri-stating the W# signal on it. The design will include it, but PB1 doesn't need it for the computer to work. W# can be driven full-time with no ill effects: the DFP simply drives the processor's internal WEN# signal which generates W# pulses. This should be fine fow now. Later, if I feel like it, I'll have Revision F of the PB1 re-printed and construct a new one with all the corrections. This is a design decision motivated by laziness too: hand-soldering Kynar wire onto SOT-23 devices with a soldering iron (and solder) meant for DIP chips isn't easy. Design Hardware PB1

Work on the ROM. Code ROM Software


Work on the ROM. Code ROM Software

Fixed numerous bugs with the emulator. Added a memory inspection feature. Code Emulator

Fixed bug with error reporting. Code Cross-Assembler


Created, rendered and uploaded video of the CFT running its first program. Posted on Google Plus and Facebook. Hardware Testing


I tracked down garbled register writes (via the DFP) to signals not being deasserted with HALT# asserted, and then to just MEM# and R# staying asserted. These signals are routed to the CFT busplane, and have bus-hold circuits, so when the Microcode Store ROMs stop driving them, the bus hold keeps them at their previous state. I fixed this by pulling up MEM#, IO#, R# and W# and adjusting the schematics. PB1 Testing

The w(rite) command seems to leave the MEM# and R# signals at an indeterminate state (~1.6V). The fill command doesn't do this though. After a fresh power cycle, the DFP can perform reads from the SRAM, fill memory with specific values and read them back. After a single w command, this is compromised. Bugs DFP Testing

At clock frequencies over 0.614 MHz (15% of the intended clock rate), incrementing the AC fails. The second counter seemingly wraps around at 127 or 255. The latter is clearly a carry propagation issue, but I'm not sure what the former is. The AC carry chain works fine at 0.614 MHz, and the PC carry chain works fine at 4 MHz. Bugs PB2 Testing

Write signal generation works, but once the signal is released it slowly curves back to +5V over the course of around 400 ns. This looks like the normal waveform shape for an open drain circuit, just horrendously elongated, possibly because of the parasitic capacitance of the backplane. I need a totem-pole driver for W#, so it's back to the original plan to use a 74'1G125 single tri-state buffer. Bugs PB1 Testing

The CFT processor has executed its first two programs, designed to operate without an ALU (which isn't yet installed). Both programs incremented the AC in tight loops (one also sent data to the front panel debugging interface). Milestone


The Control Bus ribbon cable needs to be mechanically stronger. Minor movements of cards can unplug it partially, causing various sorts of grief. Bugs PB1 Testing

Some of the control signals appearing on the front panel are mis-read by the input shift registers, breaking microcode disassembly. INCPC# is currently an issue. Bugs DFP Testing


Minor refactoring of the ROMs. Code ROM Software

August 2014


Added assembler definitions for 16550 UARTs. I always forget they're quite complex devices!. Code ROM Software


The RUNIT1 issue seems to be a short. The signal goes up to ~2.4V, but the PB0 tests out okay (10kΩ between the µ00 ROM pin and GND, >1MΩ between the pin and Vcc). The issue must be somewhere else, then (RUNIT1 is also on the control bus). Update: tracked the issue to a tiny solder bridge on DFP Board 2, the usual culprit for shoddy construction. Shockingly, with the RUNIT field operational, the computer is now working and executing a nonsensical program, including talking to the DFP itself! (PRINTx instructions being logged). Bugs PB0 Testing

Some DFP I/O instructions cause the DFP to crash, and the watchdog causes a reset. This one is a bit premature, of course. Bugs DFP Testing


If the Microcode Store is in a state when IR is being written, even with the processor halted, you can't modify the IR via the switches or debug UI. This shouldn't be the case, all the units should be idle with the processor halted, and the microcode lights certainly indicate just this (all off). Bugs PB0 Testing

When the CFT starts halted, (RAM/ROM switch set to RAM), the DFP doesn't give the processor enough clock ticks to de-assert RSTHOLD#. This should be part of the reset function (let the clock run and ensure the RESETTING state has cleared by looping until the WAIT# input is 1). Bugs DFP Testing


Signal IBUS10 does not appear to be held properly, or is shorted to ground somewhere. When the DFP writes FFFF to the IBUS and then stops driving, the IBUS changes to FBFF. Likewise, 0400 flickers between 0400 and 0000, even while being supposedly driven. Perhaps DFP Board 2 isn't driving that bit properly. This doesn't always happen, though, and all register diagnostics pass for PC, AC and IR. Bugs PB1 Testing

Sometimes, the AC diagnostics fail with the lower nybble of the AC seemingly stuck to 0. (i.e. writing FFFF, but reading back FFF0). Bugs PB2 Testing

The DFP ustep command can step multiple times (even if single stepping). Sometimes, the step ends with some lights illuminated, other times the lights are idled (and all lights on the front panel are off). Bugs DFP Testing


Coded DFP TTY driver as a proof of concept. Added NULL (sentinel) driver. Added driver abstraction and basic system call support. You can now output characters to abstract terminal devices. Code ROM Software


ROM development and fixes. Refactoring old asm directory, and started merging code into a new ROM subproject. Worked on the basic OS calls. Code ROM Software


Fixed bugs with the IRC in the C emulator. Added support for the DFP terminal using code taken directly from the DFP firmware. Lovely how code can be shared between firmware and emulator!. Code Emulator

Minor ROM development and fixes. Started work on refactoring the Forth interpreter to fit the new memory layout, OS primitives and Assembler improvements. Code ROM Software


WEN# was pulled up (by the PB0) and down (by the DFP) simultaneously. Removed the DFP resistor and good riddance. I keep finding these! The PC4 pin on PB2's IC12 counter was connected to +5V via a tiny solder bridge under the chip (too much solder paste, which is what you get when you solder with paste and no stencil). I clipped the pin, reheated the space under the chip very carefully, verified the bridge had sublimated and absorbed by pads, then re-connected the pin to the pad with a very short length of wire. Bus Writes via the processor don't seem to work. Bus reads may also be non-functional but it's difficult to test without bus writes (memory seems to initialise to &FFFF). Bugs DFP Testing


Added memory allocation functionality to the ROM. It only has bank granularity for now. Much closer to re-incorporating the Forth interpreter in the new OS framework. Code ROM Software


Added entry/exit conventions to the macro definitions. Minor work on the ROM. Code ROM Software


Fixed halting bug. DFP Firmware Testing

Loading the IR from the SR fails. This could be a firmware bug. The IR0 and IR1 (or IBUS0 and IBUS1) signals are swapped somewhere. Setting the SR for 0002 makes the IR 0001 and vice versa. Tracked down to swapped IBUS wires on the PB2. No biggie. Going through the test script for the DFP, I discovered yet another signal that was pulled up and down simultaneously: WAIT#. I'm removing the pull-down. And more of the same: some unit is still driving the IBUS with the machine halted. It's not DFP board 2, because I'm getting mismatched values when writing to the IBUS from it. PB1 doesn't use the IBUS, so the culprit must be on PB1, and specifically the AGL, Data Bus Transceiver, or numerous shorts. Update: fixed quite early. The real culprit was the control bus ribbon cable not being plugged into PB0. Yet another bug: when microstepping, the last step of a microprogram is skipped because END# seems to take effect immediately. This is probably because the µPC is reset asynchronously but incremented synchronously. Update: fixed when the PB0 ribbon cable was reconnected. The microcode control vector isn't read correctly on the DFP serial interface, but displays correctly on the panel light. The computer seems to be selecting the ROM bank on the MEM board regardless of the setting of the RAM/ROM switch on the front panel. The PC on PB2 does not increment correctly. Bit 4 is stuck on, and the PC counts between &0010-&001F inclusive. Carry aggregation issue? It could also be an issue with the front-panel buffers. Bugs DFP Testing

The ‘reset’ light lights when the RSTHOLD# signal is asserted (processor's reset state). Since resetting always runs at full speed, it may be nice to turn this light on during RESET# or RSTHOLD# assertion. A wired AND gate will do for this, and there's plenty of space available for it. DFP Design Hardware


The microcode store now works (seemingly). Various apparent issues seem to be stemming from the missing PC and AR registers. Perhaps it's time to start testing PB2. Bugs DFP Hardware Testing

When switching from Creep to Slow mode via the front switch, it often takes a while for the change to take place. This is likely a firmware bug, since the same command from a controlling computer works fine. Bugs DFP Firmware Testing


It turns out that both control signals to the IR are wrong. when the IR flip flops were replaced with latches, the WIR# active low signal should have been inverted ('573 have an active high latch enable pin). So the IR only updates its value when it's not supposed to, and it never outputs a value. An '1G04 inverter is being used to fix this. Additionally, and this is a good thing, during the patching I discovered the WIR# signal didn't in fact reach both latches. This looks like a PCB defect, and may mean there are others. Bugs DFP Hardware Setbacks Testing

IR issues fixed. The IR now displays as &FFFF without memory installed, and is routed to the µADDR vector correctly. The WIR# signal isn't generated yet though, because there's still a short or other issue with the RUNIT field in the microcode. Hardware PB1 Testing


Ported stack macros from ROM Forth to the new architecture. Code ROM Software

Fixed macro argument expansion bug. Tools


Created, rendered and uploaded video of DFP, PB0 and PB1 testing to YouTube. Posted on Google Plus and Facebook. Hardware Testing


Removed the stupidly connected LEDs from the RESET# circuitry, and the CFT finally works. The µPC is enabled and counts up on the front panel. Updated testing plan with the workings of DFP. Fixed issue with Fetch/Exec decoder (it was working fine, the DIP switches weren't set properly). Fixed issue with AB0 stuck on (the joint between the output and the pull-ups had broken, so the line was never driven down). DFP Hardware Testing

The Fetch/Exec decoder lights don't currently work. Bit 0 of the Address Bus is stuck on (seems to be DFP Board 2's fault). Potential short between RUNIT1 and RUNIT2 on PB0. Lights miswired: the microcode vector goes END, WEN, R, IO, MEM. The panel lights go END, W, R, MEM, IO (this should probably be fixed by rewiring on DFP board 1 and changing the labels on the front panel design). Bugs DFP Hardware Testing

A gorgeous, annoying bug: The part used for the Instruction Register was changed from a flip flop with clock and reset to a latch with latch enable and output enable. The location of the reset (flip-flop) and output enable (latch) signals were the same on both schematic and board, and both received the same signal: RESET#. This work with a flip-flop (resetting the IR), but fails on the latch (the IR only drives during reset, not always). The PB1 will thus have to receive its fourth patch. Bugs Hardware PB1 Testing

Potential LED wiring issue. RUNIT1 bit seems wrong. Bit(s) flipped or shorted somewhere?. Bugs Hardware Testing

July 2014


Added retro modes. When the computer is booted with the Switch Register holding a BCD-encoded year in the 20th Century (19xx), the computer will only enable some subsystems to emulate a typical computer from that year. Code various other cleanups and added new useful macros. Code ROM Software


Added code to decode VDU format images and blit them to the VDU. Wrote various additional parts of the boot loader code. Code ROM Software


Created a small tool to perform minimal quantisation on images and convert them to VDU format. The img2vdu tool already ostensibly does this, but its output is currently flawed. This minimal version will be integrated with it eventually. Tools

Generated the CFT logo in VDU format, suitable for assembling as part of the ROM and blitting to the VDU. Code ROM Software


Added vdu.asm include file with assembly-level descriptions of the VDU version 5 registers. Code ROM Software

Implented some more of the VDU for the JS emulator. Code Emulator

Fixed minor issues with the VDU documentation. Book Documentation


Some work on the early boot ROM. Boot banner now prints out available memory. Code ROM Software

Working on implementing banks on the CFT Assembler. Tools

Implemented much of the VDU in the JS emulator. Code Emulator


Stepped PB1 to Revision F, modified schematics and routed board (datecode 1430). Design Hardware PB1


Implemented WS state machine fixes. Located more logic errors with the state machine, and also fixed those. Again, only rewiring was necessary. A serious firmware error was also fixed, and now the processor is reset properly and goes through a perfectly valid reset sequence: the microcode store asserts the right signals, and those signals drive the processor and bus. DFP Hardware Testing

The PB1 LEDs lack transistors, so they lower the voltage on their logic lines. This was really stupid. The proposal is to remove the LEDs or hack the board to add the transistors (luckily there's enough space). Bugs DFP Hardware Testing


The WS state machine errors have been located and fixed. Luckily, only rewiring of a few signals was needed. No IC or passive component changes. DFP Hardware Testing


There seems to be an issue with the WS# signal. In this condition, the contents of the IR on the front panel ‘fade away’ (either literally fade away flickering, or lights are extinguished one by one) as if the IBUS is floating (which it shouldn't be, there are bus hold ICs in place), or WIR# is triggering. Bugs DFP Hardware Testing

The WS# issue had two parts: one, many of the WS state machine's pins weren't pulled up or down accordingly. Fixing this resolved the instability of the flip flops. Two, there appear to be serious logic errors in the WS state machine design. Bugs DFP Hardware Setbacks Testing


Last night's problem traced to POWEROK being 3.3V. Temporarily wired POWEROK to +5V and reset (including the RSTHOLD# timing) is working cleanly now. DFP Hardware Testing

The reset sequence fails because of what looks like a software bug. A manually coded RESET sequence (without the firmware fully initialising) seems to work fine. Also, there may be an issue with HALT#. Bugs DFP Hardware Testing


Patched PB1 so that W# is now an open drain signal. When asserted, it's driven by an open drain NAND gate from the Q (active high) output of write strobe state machine. When de-asserted, the line is at high impedance and pulled up by a 4.7kΩ resistor. Bus Hold and a 30Ω impedance matching resistor take care of signal conditioning. Cons Hardware PB1

Drew up testing plan for each individual unit of the processor. Hardware Testing

The Clock multiplexer (IC40) on board 1 of the DFP is receiving a garbled waveform from the MCU for FPUSTEP-IN. Possible short-circuit? FPCLKEN-IN seems to be okay. There also seems to be a lot of ringing on the longer wires, and IC40 is quite far from the MCU. Bugs DFP Hardware Testing


Redid the PB1 W# tristate patch to use a open-drain NAND gate rather than a tri-state buffer. This will be much faster (and I have single OD NAND gates in stock as well). Design Hardware PB1

Added EXTSKIP# support to the IOT instruction. I forgot about that in previous versions. Microcode revision is now 6c. Design Microcode Software


Drew up spreadsheet of all cross-board processor signals and their conditioning. This will be useful in running boards one by one. Hardware Testing


Added a little bit to the DFP documentation. Book Documentation

June 2014


Fixed numerous bugs on both DFP boards. All lights are now working properly. DFP Hardware Testing

The Data Bus enable MUX on DFP Board 2 is not putting out correct values. It may have a dry joint or short, though it seems like all pins test correctly. The theory is correct and the chip works (multiple chips tried), so something else is wrong. Bugs DFP Hardware Testing


The POWEROK signal from modern ATX power supplies uses 3.3V, not 5V. This will eventually have to be level-shifted, but the machine will likely work without it: POWEROK is only used for brownout detection, and the Atmega can detect such cases and hold down RESET#. The DFP also boots with RESET# asserted, until the MCU passes diagnostics, which is the same as waiting for the power supply to assert POWEROK. Bugs DFP Hardware Testing

The entire low order 8 bits of DR have been reversed! They are reversed on Processor Board 1 to simplify routing, and the DFP wiring is wrong. All eight signals will have to be flipped around on Board 1 of the DFP. Bugs DFP Hardware Setbacks Testing

Verified most of the front panel lights. DFP Hardware Testing


The programmable bus pull-up goes through a diode driven by an inverter (so it's at H or Z, never L). The diode produces a voltage of around 4V, which is quite marginal. Under heavy load and/or fast switching, some active-low bus signals can activate inadvertently. Need to replace the inverter and diode with a '541. It can source 35mA, and provides the same functionality. A capacitor could also help. Bugs DFP Hardware Testing


Inputs from AB0–AB3 on Board 2 were reversed! Also, AB0 was shorted and producing random values (which appeared as AB3 because of the reversal). After fixing these two issues, the Address Bus diagnostics work fully. Data Bus I/O also works, but the DB can't be tri-stated until the few remaining IC sockets on board 1 are populated. Until then, the Data Bus enable circuitry thinks the CFT is reading from the DFP and drives the Data Bus with data. DFP Hardware Testing

Using the front panel switches to set the address in standalone mode doesn't work because the PC sanity checks fail (value written is not read back correctly — naturally, because there's no PC in standalone mode). Bugs DFP Hardware Testing


Fixed memory cycle bug. DFP Hardware Testing

The least significant Address Bus nybble (AB0–AB3) seems to have some issue. Values driven are not read back correctly, and DFP bus diagnostics fail. Also, the Data Bus can't be tristated. Bugs DFP Hardware Testing


Early version of a PC-side DFP communications tool (written in Python 3.4). Code DFP Hardware

Fixed several bugs with the output shift registers (mainly missing wires). The DFP now correctly updates the OR and asserts various bus signals (some incorrectly). DFP Hardware Testing

There are some issues with the bus writes. Some bits of the control bus (namely IC35, the last SR in the chain) seem to be linked: FPRUN/FPSTOP with MEM# or IO#. This is probably a software error. Bugs DFP Hardware Testing

Some command pulses may be too short. Symptom: some reads are incorrect (e.g. 0100 becomes 0110), like the shift registers failed to shift the data between samples. This is plausible since the '165 SRs shift out MSB-first. Bugs DFP Hardware Testing


Early version of a PC-side DFP communications tool (written in Python 3.4). Code DFP Hardware

May 2014


Made the swtest command echo the value of the SR to the OR to facilitate testing the lights (and output shift registers, which are currently not working). Code DFP Firmware Hardware

Drew up testing plan for front panel lights. Bugs DFP Hardware Testing


Broke some cables near the connectors to light assembly 3. I'll have to either find the breaks and patch them somehow, or recrimp an entire new flat cable. DFP Hardware Setbacks Testing

All the light modules were installed upside down. This will necessitate updating the drilling patterns for the light assembly mounting plate. Bugs DFP Hardware Testing

IR11 isn't being pulled up (but is connected). Bugs DFP Hardware Testing

The OR resets to FFFF but the DFP 'or' command doesn't update it. This could be a software bug, or an issue with the shift register clocks. Bugs DFP Hardware Testing


The R signal was both pulled up and down, ending up at 2.5V and confusing one of the shift registers of the virtual front panel. The same was true of another two signals. Bugs DFP Hardware Testing


Fixed the lights off switch. Many of the grounding wires from the switch assembly were inadvertently connected to the lights on signal (which connects to ground when lights are on, enabling front panel LEDs). This included the power switch: turning lights off would disconnect ground, deasserting the power on signal and turning the PSU off. DFP Hardware Testing

Second testing session of the DFP. Both boards are plugged into the backplane and communicating. The MCU, both 74HC259 control chips and their inverters, as well as ten input shift registers are populated and working. Current draw is approximately 50 mA. DFP Hardware Testing

Roughly half of the switches are pulled down instead of up (16 signals in all). It was more convenient to do that with the 74HC165 shift registers because half of the pins are closer to the ground rail. The fix is less pleasing to the eye, but it works now. Bugs DFP Hardware Testing

The switch register (as sampled by the MCU) appears to have its bits reversed (switch 0 is bit 15). It's a nomenclature error, since switches were originally numbered in DEC style (the left most switch is SR0, but bit 15 of the SR). It may be a switch assembly wiring issue, but it was trivial to fix in software. Bugs DFP Hardware Testing

I inadvertently swapped the signals for the Set Address and Set Accumulator switches on the switch break-out board. Bugs DFP Hardware Testing


All of the 40-pin sockets on board 2 are upside down! It's the only way to do it, since the sockets on the other boards are right-angled ones. Unfortunately, this makes the ribbon cables a lot less tidy, but it's not impossible to connect. The DFP board 1 and board 2 connection was going to be diagonal anyway, since the sockets don't align. DFP Hardware Setbacks Testing

Made ‘round’ flat cable assemblies which are more flexible and take up less space. Cons DFP Hardware

The lights off switch apparently shorts the front panel. No harm done, the ATX power supply is protected against shorts. DFP Hardware Setbacks Testing


Seventeenth construction session for Board 1. The board has now been fully wired, with the exception of the custom peripheral lights, which will be wired on demand. Cons DFP=100 Hardware

Sounded out most of the sensitive connections and removed some duplicate pull-up/donw resistors. DFP Hardware Testing


Wired power supply harness for backplane and DFP. This one is meant for testing. The final one will be a length appropriate for the layout of the case. Case Cons Hardware

Sixteenth construction session for Board 1. The MCU is now fully wired and can be tested. Cons DFP=93 Hardware


Experimented with hardware for fixing backplane onto case. Case Cons Hardware

Fifteenth construction session for Board 1. Wiring left-over signals, cleaning up, fixing errors and installing 0805 impedance matching resistors, pull-ups and pull-downs. In some cases, replacing through-hole passives with 0805 parts. Cons DFP=91 Hardware

April 2014


Additional passives arrived. Orders


Worked on Drupal side of the Changelog publishing mechanism. Changelog Documentation Progress


Worked on Drupal side of the Changelog publishing mechanism. Changelog Documentation Progress

Preparing CFT book for publication on the web (using Drupal's Feed module to import HTML as Drupal nodes). Book Documentation Web


Created conversion/import toolchain to publish the Changelog as a progress log. Changelog Documentation Progress

March 2014


Fourteenth construction session for Board 1. Rewired the MCU and started adding impedance-matching resistors to most of its outputs. Wired shift register control signals, clocks and enables. Fully connected and tested power and ground. Board 1 is now almost ready to be tested. The remaining signals connect to the right bank of lights, and they will be connected as needed since appropriate headers will need to be made for them. Cons DFP=83 Hardware

Ordered more 30Ω 0805 resistors. Orders


More work on the case design. Case Design Hardware

Ordered hardware needed to fix the backplane in place (and provide power to it). Orders


More work on the case design. Placed the backplane and fixed design issues. Case Design Hardware


More work on the case design, with emphasis on the front panel light and switch assemblies. Case Design Hardware


Drafted key lock component in SketchUp. Case Design Hardware

Fourteenth construction session for Board 1. Wired the MFD outputs (48 wires). Cons DFP=83 Hardware


Designing a case in SketchUp to ensure all the assemblies match properly. Completed the switch assembly and drafted the backplane. Case Design Hardware


Designing a case in SketchUp to ensure all the assemblies match properly. Draw the switch assembly and various additional components. Case Design Hardware


Designing a case in SketchUp to ensure all the assemblies match properly. Drafting the front panel light assembly. Case Design Hardware


Designing a case in SketchUp to ensure all the assemblies match properly. Case Design Hardware


Thirteenth construction session for Board 1. Wired the PC (thus completing the PB2 front panel connections) and various miscellaneous signals, including passive components. Corrected more errors. Cons DFP=81 Hardware


Twelfth construction session for Board 1. Connected front panel common anodes. The front panel light assembly could now (in theory) be used!. Cons DFP=74 Hardware


Eleventh construction session for Board 1. Wired the remaining P5 and corrected various wiring errors. (388 signals total). Cons DFP=73 Hardware


Tenth construction session for Board 1. Wired the remaining P4 (the PB0 front panel connector) and debugged issues. Currently wiring connector P5 (the PB1 front panel connector, carrying the IR and a few other signals). Cons DFP=72 Hardware


Synchronised the C emulator with the current I/O map. Various minor issues fixed. The C emulator now runs the alpha bootloader ROM. Code Emulator


Work on boot loader code. Code ROM Software

Some improvements to the JS emulator. Code Web


Wrote MBU and MEM detection algorithms. Code ROM Software

Added .scope/.endscope directives to allow scoped labels (this internally reduces to anonymous namespaces). Added .longstring/.endstring directives to facilitate packing of multi-line .strp directives. Tools

February 2014


Refactoring assembler include files to use namespaces and the new, more mature coding style. Code ROM Software

Fixed issues with the assembler getting confused with forward .equ/.reg definitions. Tools


Version 2.2 of the CFT Assembler. This version introduces namespaces. Tools

Created emacs major mode for editing CFT Assembler files in the proper style. Misc


Work on the JS emulator continues. A release candidate is now ready, including an updated test ROM. Code Web

Version 2.1 of the CFT Assembler. This version introduces include paths. Tools

Improved the DFP firmware's interrupt handling. Standardised on flag values. Code DFP Firmware Hardware

Started coding early parts of the ROM. Code ROM Software


Processor, UCB and MBU emulation is now in place. Code Web


Started work on an instruction-level CFT emulato, which will become version 2. Code Web


Updated JavaScript CFT microcode-level simulator for the newest panel layout and colours. Documentation Web

Created list of CFT assemblies, wiring and parts. Documentation


Mouser order (bypass capacitors, pull-up/down resistors, Kynar® wire, NKK® key switches) arrived. Orders


Numerous small fixes to the DFP firmware. Code DFP Firmware Hardware Testing


Ninth construction session for Board 1. Wiring the remaining P4 (the PB0 front panel connector). Ran out of Kynar® wire and the replacement turned out not to be Kynar (not enough heat resistance). Cons DFP=71 Hardware

Ordered more bypass capacitors, pull-up/down resistors, Kynar® wire, and also some better-quality NKK key switches for the front panel. Orders


Implemented first DFP board self-diagnostics. Code DFP Firmware Hardware Testing

Made two slight changes to the hardware for more reliable diagnostics. DFP Design Hardware


Built more of the test/simulation framework for the DFP. Discovered and fixed some bugs. Code DFP Firmware Hardware Testing


Built more of the test/simulation framework for the DFP. Code DFP Firmware Hardware Testing


Eighth construction session for Board 1. Completed wiring of switch input socket. Cons DFP=70 Hardware


Minor changes to the VDU board design. Design Hardware VDU=100


Working on HTML version of documentation. Book Com

January 2014


Working on HTML version of documentation: build framework, macro set, style, content. Created pygments lexer for Microcode assembler, added scripts to generate images of PCBs out of Gerber files. Book Com


Working on HTML version of documentation: build framework, macro set, style, content. Book Com


Working on HTML version of documentation: interactive mode demonstration widget for VDU documentation. Book Com


Working on HTML version of documentation: build framework, macro set, style, content. Book Com


Minor changes to the VDU board. Added an extender port for optional VDU daughterboards (e.g. for a sprite engine). Design Hardware VDU=100

Working on HTML version of documentation: build framework, macro set, style, content. Book Com


Working on HTML version of documentation. Book Com


Drew new version of the datapath. Book Com

Seventh construction session for Board 1. Wired AEXT lights, AC register, plus a few miscellaneous signals. Cons DFP=66 Hardware


Second attempt to produce a hybrid PDF/HTML version of the CFT book. This one is coming along better than previous ones. It uses TeX4ht with a number of hacks to sidestep issues like colour and Unicode support and converts figures, timing diagrams and other ‘difficult’ objects into bitmaps. Book Com


Sixth construction session for Board 1. Cons DFP=63 Hardware


Fifth construction session for Board 1. Added approximately 90 pull-up/down resistors to protect CMOS input stages against operation with floating inputs (e.g. missing processor). Cons DFP=55 Hardware


Fourth construction session for Board 1. Slow work due to the complex cable routing requirements (376 signals in total, plus bus rails). Cons DFP=53 Hardware


Debugging DFP with the help of the simavr framework. Fixed bus pull-ups. Code Firmware Hardware PFP Testing

Third construction session for Board 1. Wired bus rails, started light wiring harness. Cons DFP=50 Hardware


Debugging DFP with the help of the simavr framework. The run/stop/step/microstep state machine now works properly. Code Firmware Hardware PFP Testing

Third construction session for Board 1. Wired bus rails, started light wiring harness. Cons DFP=50 Hardware


Debugging DFP with the help of the simavr framework. Code Firmware Hardware PFP Testing


Debugging DFP with the help of the simavr framework. Code Firmware Hardware PFP Testing

December 2013


Building DFP testbench with simavr. Code Firmware Hardware PFP Testing

Second construction session for Board 1. Placed sockets and bypass capacitors. Cons DFP=50 Hardware


Building DFP testbench with simavr. Code Firmware Hardware PFP Testing


Building DFP testbench with simavr. Code Firmware Hardware PFP Testing


Building DFP testbench with simavr. Code Firmware Hardware PFP Testing


Building DFP testbench with simavr. Code Firmware Hardware PFP Testing


Building DFP testbench with simavr. Code Firmware Hardware PFP Testing

Building DFP testbench with simavr. Code Firmware Hardware PFP Testing


Investigating DFP testbench with simavr. Code Firmware Hardware PFP Testing


DFP (former PFP) Firmware writing. Code Firmware Hardware PFP


DFP (former PFP) Firmware writing. Code Firmware Hardware PFP

DFP (former PFP) Firmware writing. Code Firmware Hardware PFP


DFP (former PFP) Firmware writing. Code Firmware Hardware PFP


DFP (former PFP) Firmware writing. Code Firmware Hardware PFP


DFP (former PFP) Firmware writing. Code Firmware Hardware PFP


DFP (former PFP) Firmware writing. Switched MCU to Atmega328P (from Atmega168) because the firmware will definitely need more than 16k. C is quite bloated in comparison to Assembly. There really isn't that much functionality in there. Code Firmware Hardware PFP


DFP (former PFP) Firmware writing. Code Firmware Hardware PFP


Third wiring session for board 2. Cons DFP=40 Hardware


Second wiring session for board 2. Cons DFP=20 Hardware


Initial work on board 2 of the front panel. Placed sockets, wires power rails. Started wiring. Cons DFP=10 Hardware

November 2013


Yet more work on the PFP firmware. Documented some of the reset/start/stop/step clock-synchronous state machine, coded some firmware functions to control it. Code Firmware Hardware PFP

Yet more work on the PFP firmware. Documented some of the reset/start/stop/step clock-synchronous state machine, coded some firmware functions to control it. Code Firmware Hardware PFP


Worked on the PFP firmware. Compressed strings for a better fit in the 16k MCU. Code Firmware Hardware PFP

More work on the PFP firmware. Code Firmware Hardware PFP


Completed final layout of both DFP boards. Cons DFP Hardware

Fixed dates in Changelog. Misc


Wired the switches to the switch break-out board. Cons Hardware PFP


Reworked the front panel assembly, preparing for laser cutting on acrylic. The LED modules fit on the LED module assembly, and the switches are fastened to a smaller switch sub-assembly, on spacers. The front panel fascia then attaches to the LED assembly completing the design. Design Hardware PFP

Rewired the switch side of the switch assembly with kynar wire. Cons Hardware PFP


Redesigned the front panel fascia with the key locks moved to the bottom and the µCB display to the left of the IR (so it appears as the IR MSB nybble, which it is). Design Hardware PFP

Created CFT Project logo, version 2. This is cleaner, and probably renders better on the CFT itself. Misc


Second attempt to separate the PFP into two boards. This one uses a 13 IC daughterboard. Design Hardware PFP

Wired half of the front panel switch assembly before realising the loom was laid out the wrong way. I will have to do this all over. Separated flat cable turned out to be aesthetically displeasing, anyway. The next wiring attempt will use Kynar wire. Easier to bundle into a loom and easier to deal with. The wires may terminate on a small PCB with a 50-pin female socket, which will in turn connect to the PFP board using flat cable. Cons Hardware PFP Setback


Worked on the PFP/DEB joint firmware. Code Firmware Hardware PFP

Discovered a potential race condition in the interrupt state machine: if interrupts are re-enabled right before an RTI macro, there is a very minor chance the ISR will be re-entered before it exits. Like the PDP-8, the CFT is non-reentrant, and this can cause issues. The flaw can be fixed in microcode (by finding some place to add an atomic RTI instruction), or in software, by saving the ISR return address onto a stack (the Forth Return stack is an ideal choice). The latter choice is easier, of course, although it increases interrupt latency. Design Hardware PB1 Setback


Worked on the PFP/DEB joint firmware. Code Firmware Hardware PFP


Cleaned all four processor boards. Cons Hardware

October 2013


Mouser order with PFP/DEB components arrived. The order also included Intersil 82C54 ICs needed to build the timer board and a second 16C2550 dual UART for the second half of the TTY board. I am now stocked to build the processor, PFP/DEB, interrupt controller, timer and IDE host adaptor boards. Orders

Crimped the Molex side of the front panel lights wiring loom (190 hand-crimped pins). Cons Hardware PFP


Worked on the PFP/DEB joint firmware. Code Firmware Hardware PFP

The ribbon cable I ordered on Ebay was probably lost en route. Jumped the gun and bought 10m of 50-way ribbon from the high street. The price was comparable. Orders


Programmed and labeled Flash ROMs. Cons Hardware PB3=100

Ordered additional components needed for the PFP/DEB board. Orders


Added file removal support. 2013p-10-27 AC . Code Filesystem Software

Finished construction of PB3. Cons Hardware PB3=90

Fixed TTY input bug that would only read one character per interrupt from TTY FIFOs. Code Forth ROM Software


Added file extraction support and debugged file writing. cftdt now has the essential features needed to create CFT disk images, with the exception of file deletion (which won't be needed until the CFT side can create and write files). Code Filesystem Software


Restored C filesystem code functionality: cftdt can now create Level 0, 1 and 2 files and can dump filesystem blocks in hex. Code Filesystem Software


Finished construction of PB2. Cons Hardware PB2=100


Completed schematics for amalgamated PFP & DEB board. 31 shift registers working as I/O expanders for the MCU! I can use the 6U (double-height) board and connectors previously meant to host the hand-routed PB2. Design Hardware PFP

Placed and reflowed the bottom side of PB2. Cons Hardware PB2=50

Placed and reflowed the bottom side of PB3. The top side will have to be done when the hard to find 74HC670 arrive. Cons Hardware PB3=50


Rev C PFP schematics are done, but the chip count is too high to implement on even a double-sized PCB. Now considering merging the DEB (debugging) board and PFP so that I can use a microcontroller to implement switch debouncing, lock-out and registration (12 ICs) as well as the switch operation state machine (11 ICs) and part of the start/stop state machine (7 ICs). This would remove some redundancies (e.g. both PFP and DEB implement HALT instructions), and possibly allow a ‘virtual’ front panel where the computer may be debugged and operated via a serial port. The lights would still be driven directly by hardware, of course, since the MCU would be too slow to update them all (and not have anywhere near the enough I/O pins). Design Hardware PFP Setback


Ordered components for PB2, PB3 and PFP boards, plus leftover parts for wiring the front panel itself. Orders


Worked on Front Panel schematics. Started splitting PFP into PFP controller, switch break-out board and light break-out board. All three are through-hole. Design Hardware PFP

Generated BOM for PB2, PB3 and PFP. Ordered parts for PB2, PB3 and PFP. Orders


PB3 arrived. Orders


Worked on Front Panel schematics. Design Hardware PFP


Worked on Front Panel schematics. Design Hardware PFP

September 2013


OPIF0 and FL are buffered but not connected to the front panel connector on PB0. There is a single spare pin (pin 38, previously grounded), now assigned to OPIF0 in the revision F PB0 board. This is less a problem than it seems, because both OPIF0 and FL are present on the control bus, and can be buffered and forwarded over to the control panel lights on the control panel controller (PFP) board. Hardware PB0 Setback Testing

Worked on Front Panel schematics. Design Hardware PFP

PB2 arrived. Orders


Drafted rack mount case outlines, started changing front panel to fit. Design Hardware PFP


Fixed issues with front panel assembly diagram. Design Hardware PFP

PB3 ordered. Orders


Constructed temporary front panel out of cardboard. Switches and lights are still unwired. Cons Hardware PFP


Screw and front panel hardware has arrived. Orders


Reworked VDU board from scratch, added ESD protection. Design Hardware VDU=100


Touched up PB3. Board is now ready for ordering. Rendered board. Design Hardware PB3=100

Completed prototyping board. Rendered top side of board. Design Hardware Prototyping Board=100


Populated through-hole components. Patched pull-up issue for SBL muxes. PB1 is now complete. Cons Hardware PB1=100

Ordered PB2 PCBs. Orders


Outputs of SBL muxes are not pulled up (they are tristated when idle). This implies the three-input NOR gate is superfluous too, but better safe than sorry (the external input, ENDEXT#, could be pulled up by mistake). Hardware PB1 Setback Testing

Finished top side of PB1, surface mount components only. Cons Hardware PB1=80

Drew up PB1 testing plan. Hardware PB1 Testing

Screws and front panel hardware. Orders


Wrote brief description of img2vdu output format. Documentation Extra

C Filesystem code will now compile. Clean ups. Beginnings of rewriting of the lost code. Code Filesystem Software


Uploaded video of PB0 testing to YouTube. Hardware PB0 Testing

August 2013


PB0 passes passive tests and most active tests. Hardware Milestone PB0 Testing


Drew up PB0 testing plan. Hardware PB0 Testing

Burned Microcode EEPROMs. Cons Hardware PB0=100


Placed and soldered top side of Processor Board 1. Cons Hardware PB0=100


Completed last remaining front panel boards. Tested all eight boards. Cons Hardware LED_Boards=100 Light_Assembly PFP

Placed and soldered bottom side of Processor Board 0. Cons Hardware PB0=50


Improvements to the image-to-VDU converter. First revision of the VDU image format. The converter now outputs files in this format too, either binaries or as CFT Assembler source. Tools


First revision of the image-to-VDU converter. It can handle multicolour and graphics modes for now, and procuces either image format simulating what the VDU displays, or VDU-format files in CFT Assembly or binary formats. Tools


Mouser order with PB0 and PB1 components has arrived. Orders


Recreated subversion repository with new versions of all files. Tools

Cleared PB0 and PB1 boards through customs, at the cost of two hours, eleven seperate steps in three buildings, and 75% the value of the boards in various taxes. Orders


Recreated subversion repository with new versions of all files. Tools


Data recovered. Didn't bother with the 8×8 font which represents a small amount of effort (early revisions of just the ASCII characters done). Misc

Added BOM for front panel to documentation. Documentation

Ordered SMT components for the printed versions of the CFT PB0 and PB1. Orders


Rsync accident. Accidentally deleted all files created in the past two weeks, including some filesystem code, the completed reference card, the 8×8 font and the SpeakJet® experiment code. Setback


CFT PB0 and PB1 boards arrived in Athens and are stuck in Greek customs hell. Orders Setback

Breadboarded and tested the SpeakJet® chip. Hardware SPJ Test


Minor fixes to the Data Storage (filesystem description) chapter. Book Documentation

C Filesystem code can now create, read and write Level 0 and Level 1 files. Code Filesystem Software


W# does not tri-state when the processor is halted. Will have to fix using a tri-state buffer. Design Hardware PB1 Setback

C Filesystem code can now create, read and write Level 0 files. Code Filesystem Software


Minor error corrections. Documentation Refcard

Minor fixes to the Assembler and programming model chapter. Book Documentation

First revision of an ASCII 8×8 font. Code ROM Software


Produced a bus and instruction set reference card in text, postscript and PDF. Documentation Refcard


Ordered new PB0 and PB1 boards from Smart Prototyping. Orders

July 2013


SpeakJet® chips delivered. Orders


Minor changes to the board layout. Signal conditioning. Re-rendered board. Design Hardware PB2

Minor changes to the board layout. Fixed minor issues with component/label placement. Signal conditioning. Re-rendered board. Design Hardware PB3

SpeakJet® chips ordered. Orders


Documented new Control Bus signals. Book Documentation

Minor changes to the board layout. Design Hardware PB0

Minor changes to the board layout. Signal conditioning. Re-rendered board. Design Hardware PB1


Fixed Verilog testbenches for new structures. Tests on the new control bus now pass. Design Hardware Testing

Added pull-ups/pull-downs so the board can be tested on its own. The new testing scheme involves building and testing boards PB0-3 incrementally. Design Hardware PB0

Minor changes to the board layout. Design Hardware PB1

Minor changes to the board layout. Design Hardware PB2

Minor changes to the board layout. Design Hardware PB3

Built and tested the clock generator and write strobe generation logic to verify they work as expected on real hardware. Cons Hardware PB1 Testing


More solder paste (in syringes), a manual applicator with plunger and an IR thermometer have been delivered. They should make hot-air soldering easier. Orders Tools

Finished routing PB0. Rendered result. Design Hardware PB1

Minor re-routing for amended control and expansion bus signals. Design Hardware PB2

Minor re-routing for amended control and expansion bus signals. Design Hardware PB3


Routing PB0. Design Hardware PB1


Minor routing fixes. Re-rendered. Design Hardware PB0

Placing PB1 almost from scratch. Without the unic decoders and separate microcode store connector, there's a lot more space for routing and the process is expect to be considerably less painful than previous revisions of the board. Design Hardware PB1


Finished routing revision E PB0. Board passes DRC and ERC. Rendered proofs of the board. Design Hardware PB0


Routing revision E with the new layout and no microcode connector. Design Hardware PB0


Realised need for pull-ups for all input signals. Added pull-ups. Since I'm reworking PB0 anyway, investigating removing the microcode store connector altogether, in favour of the control bus. Most of the signals are there anyway. However, this requires moving the unit decoders to PB0 too. Added SMT resistor arrays for impedance matching on all outputs. Design Hardware PB0

Reworking PB1 to remove microcode store connector in favour of the control bus. Through-hole resistor nets to be removed in favour of SMT resistor arrays. Design Hardware PB1

PB2 was not receiving DEC# signal from the microcode store because DEC# was never assigned a control bus pin! Reworked control bus to add this. Merged INCCPL# and DECCPL# signals into ACCPL# using an AND gate on PB2. Design Hardware PB2 Setback

PB3 must be reworked to incorporate the merged INCCPL# and DECCPL# signals. This may save up to two gates. Design Hardware PB3

Reworking signals needed for the control bus, merging in signals used in the microcode connector with a view to removing it altogether. Control_Bus Design Hardware

Refactored Verilog code to account for changes in processor design. Design Hardware Sim


Investigating use of the DS1805 I²C-programmable clock generator on PB1. It'll allow the processor frequency to be changed for testing, and also takes up less space than a traditional oscillator. Design Hardware PB1

Investigating use of the DS1805L I²C-programmable clock generator on the VDU. The CPLD can program it via I²C and we can support arbitrary pixel clocks up to 33 MHz (pixel clocks are currently half the frequency of the CPLD clock). Mostly, it'll be able to generate lower frequencies to drive, for instance, old-style 15 kHz RGB monitors (at lower resolutions, of course). Design Hardware VDU


The wrong version of PB0 was printed! The CAM job processed the right files (revision C), but the ZIP script zipped up revision A, even after I verified the Gerbers. I'll need to re-order PB0. On the upside, I fixed the IRQS# bug in the µCB extension and rerouted the board using the TSSOP-48 16-bit buffers I ordered by mistake. The new PB0 passes ERC and DRC and has been rendered front and back, as usual. Design Hardware PB0 Routing Setback


PB1 routing. Design Hardware PB1 Routing

Processor Board 0 (the Microcode Store) PCBs arrive. Milestones Orders


PB1 routing. Design Hardware PB1 Routing


Updated Changelog with entries from Subversion log. Changelog Documentation Progress

PB1 routing. Considering re-routing from scratch. Design Hardware PB1 Routing


Generated Changelog file using entries from Facebook page. Changelog Documentation Progress


Bug discovered in PB0 µCB extension: executing the Interrupt Service Routing cancels any temporarily set bank. Proposed fix is to AND the INT input to the microcode store with the temporary bank enable, making a temporary bank switch and the instruction following it an atomic operation (as far as interrupts are concerned). The design for this is still not in place and will have to be patched in because the PB0 boards have already been shipped. Design Hardware PB0 Setback

PB1 routing. Design Hardware PB1 Routing=80

Changed semantics of MBU's enable bit. 0 is on, 1 is off. Makes it faster to change banks (no additional OR is required). Makes it harder to turn off banking, which is a very uncommon operation. Design PB2 Schematic

Synchronised emulator with new I/O map. Code Emulator

Rewrote MBU emulation. Code Emulator

Changed code to accommodate new I/O map. Code Forth ROM Software


6 of 8 boards populated with SMD parts. Cons Hardware LED_Boards=70 Light_Assembly PFP


Drew panel assembly cross-section. Design Hardware PFP=80

PB1 routing. Design Hardware PB1 Routing

June 2013


Spray-painted switch paddles for front panel switches. Cons Hardware Light_Assembly PFP Switch_Assembly

PB1 routing. Design Hardware PB1 Routing


Mouser order with components for the panel and latest PB0 arrived. Orders

I ordered the wrong package for the rather expensive 16-bit buffers used for the front panel. They're TSSOP48 which is smaller than SSOP48 (which is small enough). A few single-gate ICs were ordered in three-input versions rather than two-input versions. Will work into incorporating the mis-ordered parts into other boards. Orders Setback


Renamed processor boards. The boards are now PB0 (formerly the Microcode Board), PB1 (Processor Board A), PB2 (Processor Board B) and PB3 (Processor Board C). Book Documentation Meta

Moved entire sequencer to PB0. Rerouted. Design Hardware PB0

Produced CAM jobs for printing PB0. Proofed land patterns for SOIC ICs, 0805 passives and other components. Hardware PB0 Prep

Ordered PB0 boards from Smart Prototyping. Orders

Designing layout of light assembly using LED modules. Design Hardware Light_Assembly PFP


First PCBs (the front panel modules) arrive from Smart Prototyping and they look good. Got a yield of thirteen boards, while ten were ordered. Milestones Orders

Designing layout of light assembly using LED modules. Design Hardware Light_Assembly PFP


Writing a PC-side tool to manage and access CFT disk images, disk labels and filesystems. Developing the algorithms will provide a basis for coding them in CFT Assembly for inclusion in the ROM. Tools

May 2013


‘Processor Board C’ routed. Design Hardware PB3


A batch of front panel modules is on its way from China. The boards serve as a test of the fab facility's quality. Orders


Touched up design of ‘Processor Board B’, the register board. Rendered the board. Design Hardware PB2

Preparing Microcode Board for printing. Routed another version, rendered result. Design Hardware PB0


Spent five hours wiring up the register board. Decided 900 nets will take too long to wire and will make issues almost impossible to find and fix. Resigned to making PCBs of all four processor boards. Cons Hardware PB2 Setback


Verilog verification of processor passes test suite. Design Hardware Sim Testing


Revived the idea of the panel LED assembly on PCB modules. Eight single-sided modules of 4×5 LEDs were designed. This is Revision C of the front panel module. Design Hardware LED_Boards Light_Assembly PFP


Microcode card job files ready for fabrication. Hardware PB0 Prep

April 2013


Ordered Digital Storage Oscilloscope. Tools


Routing PB2 (as ‘Processor board B’, the register board) on a 16×10cm EuroBoard. Design Hardware PB2

March 2013


Rewrote tests for the hardware, including new ones to cover design changes. Hardware now covered 100% with exhaustive tests. Testing revealed numerous annoying hardware bugs that were fixed easily. Design Hardware Sim Testing


Coded 32-bit division. Whoever wrote a 24-bit division routine for a PDP-8 is an unsung hero. If my assembler didn't have macros I'd have gone crazy. Code ROM Software


Glitch found while testing processor as a whole. Design Hardware Setback Testing

February 2013


Microcode personality board renamed to Microcode Board, hosts microcode store and µBC extension. Cleaned up schematics and routed Rev A. Rendered routed board. Design Hardware PB0


Auto-Index Logic bug found. Any Indirect mode instruction immediately following an Autoindex instruction changes into an Autoindex instruction too, no matter what location is being accessed. Hardware PB1 Setback Test


Toyed with the idea of a Bowen-style reference card. Documentation Refcard

GeSHI PHP syntax highlighter mode for CFT Assembly. Documentation Web


Wrote CFT microcode-level simulator in Javascript. Shows Front Panel and simple output device, runs considerably slower than real hardware. Documentation Web


Updated to Microcode version 6. Code Microcode Software


Microcode version 6 being designed with additional instructions: JMPII (doubly-indirect JUMP, i.e. the Forth ENTER instruction) and POP to help with Forth. Design Microcode Software

Georgios Fountis donated a book on advanced Forth techniques. Misc


Worked on emulator, fixing issues and refactoring code. Version 0.7 now available. Code Emulator

January 2013


Started layout of PB2 as ‘Processor Board B’ on double-width Euroboard. Cons Hardware PB1


VDU fully synehtesisable and tested using JTAG interface. Video of JTAG-based demo uploaded to YouTube. Design Hardware Sim VDU


Added VDU support for SDRAM. Not needed for final project, but necessary to test the VDU on the dev board (which has no SRAM memory). Design Hardware Sim VDU

Design changed to use 640×480 resolution rather than initial 640×400 because of better support from available monitors. VDU now offers 40×30 and 80×30 text, and high resolution graphics up to 640×480. Design Hardware VDU

December 2012


VDU design now partly synthesisable. Testing on a physical Terasic® DE-0 Nano board with an Altera® FPGA. First test patterns generated at 640×400 with 64 colours. Design Hardware Sim VDU


The VDU board passes ERC and DRC tests. Design Hardware Sim VDU

Rendered Altera® CPLD VDU board revision E with PS/2 and Sun keyboard/mouse ports. Design Hardware VDU


The CFT Book is now 381 pages long and includes documentation on the VDU. Book Documentation


Implemented VDU in emulator for feasibility testing. It works well. Coding Emulator Sim

Altera® CPLD version of the VDU simulating cleanly. Design Hardware VDU

November 2012


Debugged and simulated VDU design. Design Hardware VDU

Xilinx® software is getting in the way and crashing on Linux. Design Hardware VDU

VDU design will not fit the chosen Xilinx® CPLD part, so 5V tolerance is no longer an option. Switched camps using an Altera® CP9500XL CPLD. Design Hardware Setback VDU


Horizontal phase control circuit allows for smooth horizontal scrolling. Design Hardware VDU


Verified VDU design fits a Xilinx® XC95288XL CPLD. Design Hardware VDU


Simulated VDU CPLD generating correct 40-column test pattern. Design Hardware Sim VDU

Split-screen working. Design Hardware Sim VDU


Timing tolerances are too tight for 74HC family. VDU card switched to Xilinx® CPLD, discrete logic abandoned. Design Hardware Setback VDU

CPLD-based VDU card schematics and routing. Design Hardware VDU

First rendering of VDU card. Design Hardware VDU


Debugging timing issues. Design Hardware VDU

October 2012


Simulated test of cassette tape encoding. The encoding is similar to Sinclair's and sounds much like a faster version of the ZX-Spectrum's tape encoding. Design Hardware IOB


First VDU image displaying in simulations. Design Hardware Milestone Sim VDU


Verilog simulations of parts of the VDU. Design Hardware Sim VDU


Created monitor emulator to verify VDU designs on. Design Hardware Sim Tools VDU

Verilog simulations of parts of the VDU. Design Hardware VDU


Initial Verilog simulations of parts of the VDU. Design Hardware VDU


Designed cassette tape interface to add to the IO Board. Design Hardware IOB


Worked on documentation. Book Documentation


Documented filesystem structures. Documentation Filesystem Software

First draft of a floppy controller board. Design FDC Hardware

September 2012


Drafting schematics of the VDU board. Design Hardware VDU


First appearance of the CFT Book as a single entity, rather than the various separate guides. The initial version is 309 pages long. Book Documentation


Potential transmission-line and termination issues with backplane mandate a digital storage oscilloscope for debugging. Construction temporarily on hold while I budget. Setback Tools


Created first edition of CFT Progress Poster/Infographic. Documentation Progress


Programmatically extracted signals needed for the control bus using Python script and the processor's netlist. Control_Bus Design Hardware


Backplane termination resistors burn parts of DEB and MEM boards. Replaced dead memory on MEM board, but one I²C GPIO chip now missing from DEB board. Hardware MEM Setback Testing

August 2012


Completed construction of the MEM board. 512kW of flash ROM and RAM, debugging LEDs and pull-down resistors for when MBU is missing. Cons Hardware MEM=100


MOS termination resistors on backplane too strong for CMOS drivers, getting strange readings from DEB board. Resistors getting unacceptably hot in operation. Cons DEB Hardware Setback


Completed first revision of the DEB firmware. Code DEB Firmware=100 Hardware


Completed construction of DEB card. Cons DEB=100 Hardware


Updated Flashprog software. Added PLCC32 socket for CFT Flash ROMs. Tools


AY-3-8910 chips arrive. Orders


Updated specification for the DEB board. DEB Documentation Hardware


Added VDU support to the emulator. Coded various other improvements. Code Emulator


First round of components ordered. Milestone Orders


Designed layout templates for double-width DIP boards. Documentation Hardware

Laid out PB1 as ‘Processor Board A’ with DIP components. Design Hardware PB1

Laid out PB2 as ‘Processor Board B’ with DIP components. Design Hardware PB2

Laid out PB3 as ‘Processor Board C’ with DIP components. Design Hardware PB3


Finished design of debugging board. DEB Design Hardware

Rendered DEB board. DEB Documentation Hardware

Rendered DEB board. DEB Documentation Hardware


Started @CFTProject twitter account. Documentation Web

July 2012


Drafted specification for compact music file format to help ripping music from Z80 executables to compact files for the CFT. Documentation Hardware SND


First draft of sound card incorporating an GI AY-3-8910 chip. Design Hardware SND


Simplified clock generator. Design Hardware PB0


Added Flickr set, opened it to the public. Documentation Web


Designed front panel layout version 4 (4U, three bank). Design Hardware PFP


Updated front panel specification. Documentation Hardware PFP


Initial design of a VDU board. Design Hardware VDU

May 2012


Completed DOES> implementation. Code Forth ROM Software


Many changes to the word set. Code Forth ROM Software

Added more screenshots. Documentation Gallery

Released Revision F of the Programming Guide. Book Documentation

April 2012


Additional changes to implement more words and more IDE support. Code Forth ROM Software

IDE emulation improvements. Minor changes to support updated hardware. Added more debugging info. Code Emulator

Minor bug fixes and .reg directive support. Code Cross-Assembler


Major changes to the ROM to facilitate device detection/initialisation etc. Code ROM Software

Major changes to add device drivers, clean up code and implement banked memory. Code Emulator


Autoindex bug located in the IN instruction. Fixed. Code Microcode Setback Software

Work on attaching new I/O devices. Code Emulator

Numerous additions to dictionary. IDE test code. Minor changes to the user area. Code Forth ROM Software


Considerable amounts of work done. Compiler is now in place. Code Forth ROM Software


Forth 83 multiple vocabulary support is now in place. Code Forth ROM Software


More vocabulary work. Renumbering to fit ONLY vocabulary. Code Forth ROM Software


Major additions for debugging, testing. Added compiler words, some defining words and more vocabulary functionality. Code Forth ROM Software


Most of the interpreter is now in place, including error handling. Code Forth ROM Software

Fixed issues with excessive CPU power due to tight select(2) loops. Added more I/O. Fixed fetch/execute cycle detection. Code Emulator

March 2012


Major changes to the dictionary structure. Coded user area, added some vocabulary support. Lots of refactoring. Code Forth ROM Software


Various bits of Forth work. Code Forth ROM Software


Implemented algorithms and unit tests for unsigned, symmetric and floored division in 16 and 32 bits. For now, Forth algorithm tests are shared with the Verilog tests (and executed with the Verilog simulator). Code Forth ROM Software

Bug fixes and implementation of various Forth words. Code Forth ROM Software


Added more hardware tests. Design Hardware Testing

Imported mkskiptable, meant to speed up minor operation instructions. The functionality is currently too complex, so not used. Design Hardware

Bug fixes and Forth work. Code ROM Software


Created Facebook page. Documentation Web

More Forth primitives. Code reorganisation. Code Forth ROM Software

First OS traps added. Code ROM Software


Cleaning up Subversion repository. Removing temporary files. Tools

Coded core ROM Forth words (and then some). Code Forth ROM Software

February 2012


Completed CFT schematic collection into a very large Eagle file. This will help keep signal names constant, and will eventually aid DRC. Design Hardware


Fixed ALU bugs. Recoded Verilog ROM-ALU to handle the new ALU design. Design Hardware

Updated schematics, fixing numerous issues (including the ALU one). Design Hardware

Added batch tests for the ALU. Design Hardware Testing

Added Forth documentation (external to the project). Documentation Extra

Added FlashForth distribution (also external). Documentation Extra

Work on the filesystem code. Code Filesystem Software


Corrected issues with the ROM-based ALU. Design Hardware

Coded ALU test benches in Verilog. Design Hardware Testing


Drafting timer layout. CTN Design Hardware

January 2012


Considerable amount of work on the front panel controller. Controller Design Hardware PFP

Worked on the clock generator. Design Hardware


SMD test of front panel controller. Superseded design, now using new version of front panel controller. Controller Design Hardware PFP

Various changes and corrections to the front panel. itself. Design Hardware PFP

Added PNG files to the gallery. Documentation Gallery


Added functionality to extract bills of materials from Eagle schematics. Tools

Added BOM for front panel to documentation. Book Documentation

Added external documents useful for the development of the project (datasheets, etc). Documentation Extra

First filesystem experiments. Code Filesystem Software

Front Panel version 2 (rev B). Design Hardware PFP

Front Panel Bill of Materials generated. Documentation Hardware PFP

December 2011


Cleaned up crud entries from Subversion repository. Tools


Added macro and file inclusion support. Code Cross-Assembler

Slight changes to Eagle3D board rendering options. Tools

Rendered front panel controller. Controller Design Hardware PFP


Completed first revision of Front Panel Controller board. Controller Design Hardware PFP


Additional work on the front panel. Design Hardware PFP


More work on the front panel and its documentation. Design Hardware PFP


Further design and verification work on the panel. Design Hardware PFP


First release candidate of the front panel. Design Hardware PFP


First draft of the front panel. Design Hardware PFP


Worked on Front Panel schematics. Design Hardware PFP

November 2011


Removed VHDL support and relevant directories. The project has been using Verilog for verification for a while. Tools

Created CFT Project logo. Misc


Released FlashProg hardware and software design. Tools

October 2011


Released mcasm (the Microcode Assembler). Tools


Released ROMtools, a Python library to generate complex function tables on multiple ROMs. This is used to generate the ALU tables. Tools

September 2011


More changes to the hardware and PCBs. Design Hardware

August 2011


Changes to PCBs for new hardware style. Design Hardware


Switched to ROM-based ALU. Design Hardware


Many changes to the hardware design. Design Hardware

March 2011


Major changes to support autoincrement mode, fix issues with the L flag (excessive toggling), rework microcode, uaddr vector, control vector, register types, etc. Design Hardware

Autoincrement now supported in LOAD. Design Microcode Software

Playing around with Eagle schematics as a very early feasibility study. Design Hardware


Created Subversion repository. Initial import of pre-existing code and data. Tools

Removed Page Register from CPU design. Design Hardware

Changed MAR to '193-based register. Design Hardware

February 2011


Earliest version of the ‘simple 16-bit CPU’ description, a direct descendant of the Fungus CPU. Still references 18-bit registers (like Fungus). Design Hardware

January 2011


Earliest draft version of the ‘memory mapped stack machine’ CPU description referencing a PDP-8-like design, but with an 8 bit word. Design Hardware